LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches Proceedings Article
In: Proceedings of the 24th International Conference on VLSI Design, pp. 298-303, IEEE Computer Society, 2011.
Fast and Energy-Efficient Constant-Coefficient FIR Filters Using Residue Number System Proceedings Article
In: Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2011.
B2P2: bounds based procedure placement for instruction TLB power reduction in embedded systems Proceedings Article
In: Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems(SCOPES), pp. 2:1-2:10, 2010, (ISBN 978-1-4503-0084-1).
Reducing Functional Unit Power Consumption and its Variation using Leakage Sensors Journal Article
In: IEEE TVLSI : IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 6, pp. 988-997, 2010.
Power-Accuracy Tradeoffs in Human Activity Transition Detection Proceedings Article
In: Proceedings of the 2010 International Conference on Design Automation and Test in Europe (DATE), 2010.
Power-Efficient System Design Book
1st edition, Springer, 2010.
Code Transformations for TLB Power Reduction Journal Article
In: International Journal of Parallel Programming, vol. 38, no. 3-4, pp. 254-276, 2010, (ISSN 0885-7458).
Basic Low Power Digital Design Book Chapter
In: Power-efficient System Design, no. 978-1-4419-6387-1, Chapter 2, pp. 11-39, Springer US, 2010.
Power Aware Operating Systems, Compilers, and Application Software Book Chapter
In: Power-efficient System Design, no. 978-1-4419-6387-1, Chapter 5, pp. 139-181, Springer US, 2010.
Exploiting residue number system for power-efficient digital signal processing in embedded processors Proceedings Article
In: CASES '09: Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems, pp. 19-28, 2009, (ISBN 978-1-60558-626-7).
Code Transformations for TLB Power Reduction Proceedings Article
In: VLSID '09: Proceedings of the International Conference on VLSI Design, pp. 413-418, 2009, (ISBN 978-0-7695-3506-7).
Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, no. 3, pp. 461-466, 2009, (ISSN 0278-0070).
Residue number system enhancements for programmable processors Masters Thesis
School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009.
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors Proceedings Article
In: VLSID '08: Proceedings of the 21st International Conference on VLSI Design, pp. 421-427, 2008, (ISBN 0-7695-3083-4).
Power Reduction of Functional Units Considering Temperature and Process Variations Proceedings Article
In: VLSID'08: Proceedings of the 21st International Conference on VLSI Design, pp. 533–539, IEEE Computer Society, Washington, DC, USA, 2008, (ISBN 0-7695-3083-4).
Temperature and Process Variations aware Power Gating of Functional Units Proceedings Article
In: VLSID '08: Proceedings of the 21st International Conference on VLSI Design, pp. 515-520, 2008, (ISBN 0-7695-3083-4).
Smart driver for power reduction in next generation bistable electrophoretic display technology Proceedings Article
In: CODES+ISSS '07: Proceedings of international conference on Hardware/software codesign and system synthesis, pp. 197-202, 2007, (ISBN 978-1-59593-824-4).
Compilation techniques for energy reduction in horizontally partitioned cache architectures Proceedings Article
In: CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, pp. 90-96, 2005, (ISBN 1-59593-149-X).