Shail Dave; Tony Nowatzki; Aviral Shrivastava
Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis Proceedings Article
In: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2024, (Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)).
Abstract | BibTeX | Tags: Accelerated Computing, Machine Learning, Machine Learning Accelerators | Links:
@inproceedings{Dave2024ASPLOS,
title = {Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis},
author = {Shail Dave and Tony Nowatzki and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Dave2024ASPLOS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Dave2024ASPLOS.pptx, slides
https://mpslab-asu.github.io/publications/posters/Dave2024ASPLOS.pdf, poster
https://youtu.be/y-F1Cp66_oQ, teaser},
year = {2024},
date = {2024-04-02},
urldate = {2024-04-02},
booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)},
abstract = {Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE – a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an
API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.},
note = {Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)},
keywords = {Accelerated Computing, Machine Learning, Machine Learning Accelerators},
pubstate = {published},
tppubtype = {inproceedings}
}
API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.
Shail Dave; Aviral Shrivastava
Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures Conference
Proceedings of the TECHCON, 2023.
Abstract | BibTeX | Tags: Accelerated Computing, Machine Learning, Machine Learning Accelerators | Links:
@conference{Dave2023TECHCON,
title = {Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures},
author = {Shail Dave and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Dave2023TECHCON.pdf, pdf},
year = {2023},
date = {2023-09-11},
urldate = {2023-09-11},
booktitle = {Proceedings of the TECHCON},
abstract = {Domain-specific architectures (DSAs) are increasingly designed to efficiently process a variety of workloads, such as deep learning, linear algebra, and graph analytics. Most research efforts have focused on proposing new DSAs or efficiently exploring hardware/software designs of previously proposed architecture templates. Recent architectural modeling or simulation frameworks for DSAs can analyze execution costs, e.g., for a limited architectural templates for dense DNNs such as systolic arrays or a spatial architecture with an array of processing elements and 3-level memory hierarchy. However, they are manually developed by domain-experts, containing several 1000s of lines-of-code, and extending them for characterizing new architectures is infeasible, such as DSAs for sparse DNNs. Further, the lack of automated architecture-level execution modeling limits the design space of novel architectures that can be explored/optimized, affecting overall efficiency of solutions, and it delays time-to-market with low sustainability of design process.
To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.},
keywords = {Accelerated Computing, Machine Learning, Machine Learning Accelerators},
pubstate = {published},
tppubtype = {conference}
}
To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.
Mohammadreza Mehrabian; Mohammad Khayatian; Aviral Shrivastava; Patricia Derler; Hugo Andrade
A run-time verification method with consideration of uncertainties for cyber-physical systems Journal Article
In: Microprocessors and Microsystems, vol. 101, 2023.
BibTeX | Tags: CPS, Timing in Cyber-Physical Systems | Links:
@article{Mehrabian2023MICPRO,
title = {A run-time verification method with consideration of uncertainties for cyber-physical systems},
author = {Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and Patricia Derler and Hugo Andrade},
url = {https://www.sciencedirect.com/science/article/pii/S0141933123001345, paper},
year = {2023},
date = {2023-06-22},
journal = {Microprocessors and Microsystems},
volume = {101},
keywords = {CPS, Timing in Cyber-Physical Systems},
pubstate = {published},
tppubtype = {article}
}
Yi Hu; Chaoran Zhang; Edward Andert; Harshul Singh; Aviral Shrivastava; James Laudon; Yanqi Zhou; Bob Iannucci; Carlee Joe-Wong
GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing Proceedings Article
In: Proceedings of the Sixth Conference on Machine Learning and Systems (MLSys), 2023.
BibTeX | Tags: Accelerated Computing, Machine Learning, Machine Learning Accelerators, Real-Time Systems
@inproceedings{Hu2023MLSYS,
title = {GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing},
author = {Yi Hu and Chaoran Zhang and Edward Andert and Harshul Singh and Aviral Shrivastava and James Laudon and Yanqi Zhou and Bob Iannucci and Carlee Joe-Wong},
year = {2023},
date = {2023-06-04},
urldate = {2023-06-04},
booktitle = {Proceedings of the Sixth Conference on Machine Learning and Systems (MLSys)},
keywords = {Accelerated Computing, Machine Learning, Machine Learning Accelerators, Real-Time Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
Matthew Szeto
B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles Masters Thesis
Arizona State University, 2023.
BibTeX | Tags: Intelligent Transportation, Intersection Management | Links:
@mastersthesis{Szeto2023THESIS,
title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles},
author = {Matthew Szeto},
url = {https://mpslab-asu.github.io/publications/papers/Szeto2023THESIS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides},
year = {2023},
date = {2023-05-08},
urldate = {2023-05-08},
school = {Arizona State University},
keywords = {Intelligent Transportation, Intersection Management},
pubstate = {published},
tppubtype = {mastersthesis}
}
Behnaz Ranjbar; Florian Klemme; Paul R. Genssler; Hussam Amrouch; Jinhyo Jung; Shail Dave; Hwisoo So; Kyongwoo Lee; Aviral Shrivastava; Ji-Yung Lin; Pieter Weckx; Subrat Mishra; Francky Catthoor; Dwaipayan Biswas; Akash Kumar
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level Proceedings Article
In: Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE), 2023.
BibTeX | Tags: Efficient Embedded Computing, Error Correction, Error Resilience, Machine Learning, Machine Learning Accelerators, Soft Error | Links:
@inproceedings{Ranjbar2023DATE,
title = {Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level},
author = {Behnaz Ranjbar and Florian Klemme and Paul R. Genssler and Hussam Amrouch and Jinhyo Jung and Shail Dave and Hwisoo So and Kyongwoo Lee and Aviral Shrivastava and Ji-Yung Lin and Pieter Weckx and Subrat Mishra and Francky Catthoor and Dwaipayan Biswas and Akash Kumar},
url = {https://mpslab-asu.github.io/publications/papers/Ranjbar2023DATE.pdf, paper
https://mpslab-asu.github.io/publications/slides/Ranjbar2023DATE.pptx, slides},
year = {2023},
date = {2023-04-17},
urldate = {2023-04-17},
booktitle = {Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE)},
keywords = {Efficient Embedded Computing, Error Correction, Error Resilience, Machine Learning, Machine Learning Accelerators, Soft Error},
pubstate = {published},
tppubtype = {inproceedings}
}
Sanggu Park; Edward Andert; Aviral Shrivastava
Blame-Free Motion Planning in Hybrid Traffic Journal Article
In: IEEE Transactions on Intelligent Vehicles, pp. 1-10, 2023.
BibTeX | Tags: Intelligent Transportation, Intersection Management | Links:
@article{ParkTIV2023,
title = {Blame-Free Motion Planning in Hybrid Traffic},
author = {Sanggu Park and Edward Andert and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Park2023TIV.pdf, paper},
year = {2023},
date = {2023-04-05},
urldate = {2023-04-05},
journal = {IEEE Transactions on Intelligent Vehicles},
pages = {1-10},
keywords = {Intelligent Transportation, Intersection Management},
pubstate = {published},
tppubtype = {article}
}
Moslem Didehban; Hwisoo So; Prudhvi Gali; Aviral Shrivastava; Kyoungwoo Lee
Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication Journal Article
In: IEEE Transactions on Dependable and Secure Computing, vol. 1, pp. 1-16, 2023.
Abstract | BibTeX | Tags: Error Resilience, Soft Error | Links:
@article{Didehban2023TDSC,
title = {Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication},
author = {Moslem Didehban; Hwisoo So; Prudhvi Gali; Aviral Shrivastava; Kyoungwoo Lee},
url = {https://mpslab-asu.github.io/publications/papers/Didehban2023TDSC.pdf, paper},
year = {2023},
date = {2023-02-14},
urldate = {2023-02-14},
journal = {IEEE Transactions on Dependable and Secure Computing},
volume = {1},
pages = {1-16},
abstract = {Transient faults or soft errors are considered one of the most daunting reliability challenges for microprocessors. Software solutions for soft error protection are attractive because they can provide flexible and effective error protection. For instance, nZDC [1] state-of-the-art instruction duplication error protection scheme achieves a high degree of error detection by verifying the results of memory write operations and utilizes an effective control-flow checking mechanism. However, nZDC control-flow checking mechanism is architecture-dependent and suffers from some vulnerability holes. In this work, we address these issues by substituting nZDC control-flow checking mechanism with a general (ISA-independent) scheme and propose two transformations, coarse-grained scheduling, and asymmetric control-flow signatures, for hard-to-detect control flow errors. Fault injection experiments on different hardware components of synthesizable Verilog description of an OpenRISC-based microprocessor reveal that the proposed transformation shows 85% less silent data corruptions compared to nZDC. In addition, programs protected by the proposed scheme run on average around 37% faster than nZDC-protected programs.},
keywords = {Error Resilience, Soft Error},
pubstate = {published},
tppubtype = {article}
}
Aviral Shrivastava; Xiaobo Sharon Hu
Report on the 2022 Embedded Systems Week (ESWEEK) Journal Article
In: IEEE Design & Test, vol. 40, iss. 1, pp. 108-111, 2023.
Abstract | BibTeX | Tags: Accelerated Computing, CPS, Efficient Embedded Computing, Error Resilience, Machine Learning Accelerators, Real-Time Systems | Links:
@article{Shrivastava2023D&T,
title = {Report on the 2022 Embedded Systems Week (ESWEEK)},
author = {Aviral Shrivastava; Xiaobo Sharon Hu},
url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2023D&T.pdf, pdf},
year = {2023},
date = {2023-01-23},
urldate = {2023-01-23},
journal = {IEEE Design & Test},
volume = {40},
issue = {1},
pages = {108-111},
abstract = {Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES); the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS); and the International Conference on Embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.},
keywords = {Accelerated Computing, CPS, Efficient Embedded Computing, Error Resilience, Machine Learning Accelerators, Real-Time Systems},
pubstate = {published},
tppubtype = {article}
}
Quoc Long Vinh Ta
COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops Masters Thesis
Arizona State University, 2022.
BibTeX | Tags: Accelerated Computing, CGRA | Links:
@mastersthesis{Ta2022THESIS,
title = {COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops},
author = {Quoc Long Vinh Ta},
url = {https://mpslab-asu.github.io/publications/papers/Ta2022THESIS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Ta2022THESIS.pptx, slides
},
year = {2022},
date = {2022-12-08},
urldate = {2022-12-08},
school = {Arizona State University},
keywords = {Accelerated Computing, CGRA},
pubstate = {published},
tppubtype = {mastersthesis}
}
Edward Andert; Aviral Shrivastava
Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs Proceedings Article
In: Proceedings of the IEEE 25th International Conference on Intelligent Transportation Systems (ITSC), IEEE 2022.
BibTeX | Tags: Intelligent Transportation | Links:
@inproceedings{Andert2022ITSC,
title = {Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs},
author = {Edward Andert and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Andert2022ITSC.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Andert2022ITSC.pptx, slides},
year = {2022},
date = {2022-10-08},
urldate = {2022-10-08},
booktitle = {Proceedings of the IEEE 25th International Conference on Intelligent Transportation Systems (ITSC)},
organization = {IEEE},
keywords = {Intelligent Transportation},
pubstate = {published},
tppubtype = {inproceedings}
}
Jinhyo Jung; Yohan Ko; Hwisoo So; Kyoungwoo Lee; Aviral Shrivastava
Root cause analysis of soft-error-induced failures from hardware and software perspectives Journal Article
In: Journal of Systems Architecture (JSA), 2022.
BibTeX | Tags: Error Resilience, Soft Error | Links:
@article{Jung2022JSA,
title = {Root cause analysis of soft-error-induced failures from hardware and software perspectives},
author = {Jinhyo Jung and Yohan Ko and Hwisoo So and Kyoungwoo Lee and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Jung2022JSA.pdf, pdf
},
year = {2022},
date = {2022-07-08},
urldate = {2022-07-08},
journal = {Journal of Systems Architecture (JSA)},
keywords = {Error Resilience, Soft Error},
pubstate = {published},
tppubtype = {article}
}
Hwisoo So; Moslem Didehban; Yohan Ko; Aviral Shrivastava; Kyoungwoo Lee
EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults Journal Article
In: ACM Transactions on Architecture and Code Optimization (TACO), 2022.
BibTeX | Tags: Error Correction, Error Resilience, Soft Error | Links:
@article{So2022TACO,
title = {EXPERTISE: An Effective Software-level Redundant Multithreading Scheme against Hardware Faults},
author = {Hwisoo So and Moslem Didehban and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee},
url = {https://mpslab-asu.github.io/publications/papers/So2022TACO.pdf, paper
},
year = {2022},
date = {2022-07-05},
urldate = {2022-07-05},
journal = {ACM Transactions on Architecture and Code Optimization (TACO)},
keywords = {Error Correction, Error Resilience, Soft Error},
pubstate = {published},
tppubtype = {article}
}
Shail Dave; Aviral Shrivastava
Efficient Processing of Sparse and Compact DNN Models on Hardware Accelerators: Survey and Insights Workshop
In Annual Workshop on Sparsity in Neural Networks (SparseNN), 2022.
BibTeX | Tags: | Links:
@workshop{Dave2022SNN,
title = {Efficient Processing of Sparse and Compact DNN Models on Hardware Accelerators: Survey and Insights},
author = {Shail Dave and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/posters/Dave2022SNN.pdf, poster},
year = {2022},
date = {2022-07-01},
urldate = {2022-07-01},
booktitle = {In Annual Workshop on Sparsity in Neural Networks (SparseNN)},
keywords = {},
pubstate = {published},
tppubtype = {workshop}
}
Sanggu Park
Blame-Free Motion Planning in Hybrid Traffic Masters Thesis
Arizona State University, 2022.
BibTeX | Tags: Intelligent Transportation, Intersection Management | Links:
@mastersthesis{Park2022Thesis,
title = {Blame-Free Motion Planning in Hybrid Traffic},
author = {Sanggu Park},
url = {https://mpslab-asu.github.io/publications/papers/Park2022THESIS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Park2022THESIS.pptx, slides},
year = {2022},
date = {2022-05-11},
urldate = {2022-05-11},
school = {Arizona State University},
keywords = {Intelligent Transportation, Intersection Management},
pubstate = {published},
tppubtype = {mastersthesis}
}
Shail Dave; Alberto Marchisio; Muhammad Abdullah Hanif; Amira Guesmi; Aviral Shrivastava; Ihsen Alouani; Muhammad Shafique
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems Proceedings Article
In: Proceedings of the 2022 IEEE 40th VLSI Test Symposium (VTS), 2022.
Abstract | BibTeX | Tags: Accelerated Computing, Efficient Embedded Computing, Error Resilience, Machine Learning, Machine Learning Accelerators, Soft Error | Links:
@inproceedings{DaveVTS2022,
title = {Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems},
author = {Shail Dave and Alberto Marchisio and Muhammad Abdullah Hanif and Amira Guesmi and Aviral Shrivastava and Ihsen Alouani and Muhammad Shafique},
url = {https://mpslab-asu.github.io/publications/papers/Dave2022VTS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Dave2022VTS.pptx, slides},
year = {2022},
date = {2022-04-25},
urldate = {2022-04-25},
booktitle = {Proceedings of the 2022 IEEE 40th VLSI Test Symposium (VTS)},
abstract = {The real-world use cases of Machine Learning (ML) have exploded over the past few years. However, the current computing infrastructure is insufficient to support all real-world applications and scenarios. Apart from high efficiency requirements, modern ML systems are expected to be highly reliable against hardware failures as well as secure against adversarial and IP stealing attacks. Recent developments have also highlighted various privacy concerns. Towards trustworthy ML systems, in this work we highlight different challenges faced by the embedded systems community towards enabling efficient,
dependable and secure deployment of ML. To address these challenges, we present an agile design methodology to generate efficient, reliable and secure ML systems based on user-defined constraints and objectives.},
keywords = {Accelerated Computing, Efficient Embedded Computing, Error Resilience, Machine Learning, Machine Learning Accelerators, Soft Error},
pubstate = {published},
tppubtype = {inproceedings}
}
dependable and secure deployment of ML. To address these challenges, we present an agile design methodology to generate efficient, reliable and secure ML systems based on user-defined constraints and objectives.
Christian Cunningham
Making a Real-Time Operating System for the Raspberry Pi 2B Bachelor Thesis
Arizona State University, 2022.
BibTeX | Tags: Real-Time Systems | Links:
@bachelorthesis{CunninghamTHESIS2022,
title = {Making a Real-Time Operating System for the Raspberry Pi 2B},
author = {Christian Cunningham},
url = {https://mpslab-asu.github.io/publications/papers/Cunningham2022THESIS.pdf, thesis
https://mpslab-asu.github.io/publications/papers/Cunningham2022THESIS.pptx, slides
https://github.com/MPSLab-ASU/Jobbed, Code},
year = {2022},
date = {2022-04-09},
urldate = {2022-04-09},
school = {Arizona State University},
keywords = {Real-Time Systems},
pubstate = {published},
tppubtype = {bachelorthesis}
}
Mahesh Balasubramanian; Aviral Shrivastava
PathSeeker: A Fast Mapping Algorithm for CGRAs Proceedings Article
In: Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE), 2022.
BibTeX | Tags: Accelerated Computing, CGRA | Links:
@inproceedings{Balasubramanian2022DATE,
title = {PathSeeker: A Fast Mapping Algorithm for CGRAs},
author = {Mahesh Balasubramanian and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Balasubramanian2022DATE.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Balasubramanian2022DATE.pptx, slides},
year = {2022},
date = {2022-03-16},
urldate = {2022-03-16},
booktitle = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)},
journal = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)},
keywords = {Accelerated Computing, CGRA},
pubstate = {published},
tppubtype = {inproceedings}
}
Po-Yu Huang; Kai-Wei Liu; Zong-Lun Li; Sanggu Park; Edward Andert; Chung-Wei Lin; Aviral Shrivastava
Compatibility Checking for Autonomous Lane-Changing Assistance Systems Proceedings Article
In: Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE), 2022.
BibTeX | Tags: Intelligent Transportation, Intersection Management | Links:
@inproceedings{Huang2022DATE,
title = {Compatibility Checking for Autonomous Lane-Changing Assistance Systems},
author = {Po-Yu Huang and Kai-Wei Liu and Zong-Lun Li and Sanggu Park and Edward Andert and Chung-Wei Lin and Aviral Shrivastava },
url = {https://mpslab-asu.github.io/publications/papers/Huang2022DATE.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Huang2022DATE.pptx, slides
https://mpslab-asu.github.io/publications/slides/Huang2022DATE.pdf, poster},
year = {2022},
date = {2022-03-16},
urldate = {2022-03-16},
booktitle = {Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE)},
keywords = {Intelligent Transportation, Intersection Management},
pubstate = {published},
tppubtype = {inproceedings}
}
Mohammad Khayatian; Aviral Shrivastava; Mohammadreza Mehrabian
Systems and methods for intersection management of connected autonomous vehicles Patent
2022.
BibTeX | Tags: Intelligent Transportation, Intersection Management | Links:
@patent{KhayatianPATENT2022,
title = {Systems and methods for intersection management of connected autonomous vehicles},
author = {Mohammad Khayatian and Aviral Shrivastava and Mohammadreza Mehrabian},
url = {https://patents.google.com/patent/US11269330B2/en, Google Patents},
year = {2022},
date = {2022-03-08},
urldate = {2022-03-08},
howpublished = {https://patents.google.com/patent/US11269330B2/},
keywords = {Intelligent Transportation, Intersection Management},
pubstate = {published},
tppubtype = {patent}
}