Systems and methods for fast-mapping of coarse-grained reconfigurable arrays Patent
2024.
Systems and methods for improved mapping of computational loops on reconfigurable architectures Patent
2024.
COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops Masters Thesis
Arizona State University, 2022.
PathSeeker: A Fast Mapping Algorithm for CGRAs Proceedings Article
In: Proceedings of the 25th International Conference on Design Automation and Test in Europe (DATE), 2022.
Design Space Description Language for Automated and Comprehensive Exploration of Next-Gen Hardware Accelerators Workshop
Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), 2022, (co-located with ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS).).
Compiler Design for Accelerating Applications on Coarse-Grained Reconfigurable Architectures PhD Thesis
2021.
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights Journal Article
In: Proceedings of the IEEE (PIEEE), 2021, (arXiv: 2007.00864).
CRIMSON: Compute-intensive loop acceleration by Randomized Iterative Modulo Scheduling and Optimized Mapping on CGRAs Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
RAMP: Resource-Aware Mapping for CGRAs Proceedings Article
In: Proceedings of the 55th Annual Design Automation Conference (DAC), 2018.
LASER: A Hardware/Software Approach to Accelerate Complicated Loops on CGRAs Proceedings Article
In: Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE), 2018.
URECA: A Compiler Solution to Manage Unified Register File for CGRAs Proceedings Article
In: Proceedings of the 21st International Conference on Design Automation and Test in Europe (DATE), 2018.
Scalable Register File Architecture for CGRA Accelerators Masters Thesis
Arizona State University, 2016.
A Software Scheme for Multithreading on CGRAs Journal Article
In: ACM Transactions on Embedded Computing Systems (TECS), 2015.
Path Selection Based Acceleration of Conditionals in CGRAs Proceedings Article
In: Proceedings of the 2015 International Conference on Design Automation and Test in Europe (DATE), 2015.
Register File Organization for Coarse-Grained Reconfigurable Architectures: Compiler-Microarchitecture Perspective Masters Thesis
Arizona State University, 2014.
Path Selection Based Branching for Coarse Grained Reconfigurable Arrays Masters Thesis
Arizona State University, 2014.
Branch-Aware Loop Mapping on CGRAs Proceedings Article
In: Proceedings of the The 51st Annual Design Automation Conference on (DAC), 2014, 2014.
REGIMap: Register-aware Application Mapping on Coarse-grained Reconfigurable Architectures (CGRAs) Proceedings Article
In: Proceedings of the 50th Annual Design Automation Conference (DAC), 2013.
EPIMap: Using Epimorphism to Map Applications on CGRAs Proceedings Article
In: Proceedings of the 49th Design Automation Conference (DAC), 2012.
Improving CGRA Utilization by Enabling Multi-threading for Power-efficient Embedded Systems Masters Thesis
School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2011.