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Videos and Photos

Overview Video and Photos Documents Team Photos Videos Engineering Open House   The Turret in Action   The Effects of Parallism

Death by Kinect

Overview The Two Robots Team Members Team Contributions Documentation Pictures and Videos Project Overview The purpose of the project is to visually demonstrate in a real-time system the performance gains of leveraging the parallel processing of a many-core architecture. The system uses the performance of computation intensive computer vision algorithms to measure the speed-up between…

Documentation and Source Code

Overview Video and Photos Documents Team The project documents and source code are available from the links provided below. Presentation Click to download the Capstone Presentation Code Car https://bitbucket.org/parallelorparalyze/car Turret https://bitbucket.org/parallelorparalyze/turret   Old Documentation Fall 2011 to Spring 2012 -Final Presentation Fall 2011 to Spring 2012 – Final Poster Fall 2011 to Spring 2012 –…

Team Seek and Destroy

  Project Overview Motivation The Robots Team Members Videos Documents Project Overview The project consists of two automated robots. The first robot, the turret,  attempts to fire on the target by tracking it in real time. The second robot, the car, attempts to follow and track a person, avoid obstacles along the way . The…

Heap Data Management for LLM multi-core processor

Publications Ke Bai and Aviral Shrivastava. Heap Data Management for Limited Local Memory (LLM) Multi-core Processors. In CODES+ISSS ’10: Proceedings of the 23th international symposium on System Synthesis, ACM Press, New York, NY, USA , 2010.

Non-coherent Cache Architecture

Limited Local Memory Multi-cores Soft Error Resilience Coarse Grain Reconfigurable Arrays Non-coherent Cache Architecture Challenge Our Approach Publications Resources Challenge One of the main challenges in scaling the number of cores is scaling the memory architecture. As the number of cores on a chip increases, the design complexity and the power consumption of the cache…

Code Management for LLM multi-core processor

To facilitate this code management, the IBM Cell processor provides an overlay mechanism. In a linker script, users can specify the number of regions and the mapping of functions into regions. Functions mapped to one region are mapped to the same physical location in the limited local memory, and replace each other when called. The…