Register File Power Reduction Using Bypass Sensitive Compiler Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 6, pp. 1155-1159, 2008, (ISSN 0278-0070).
Interactive presentation: Functional and timing validation of partially bypassed processor pipelines Proceedings Article
In: DATE '07: Proceedings of the conference on Design, automation and test in Europe, pp. 1164-1169, 2007, (ISBN 978-3-9810801-2-4).
Bypass Aware Instruction Scheduling for Register File Power Reduction Proceedings Article
In: Proceedings of the conference on Language, Compilers and Tool support for Embedded Systems, pp. 173-181, 2006, (ISBN 0362-1340).
Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors Proceedings Article
In: DATE '06: Proceedings of the conference on Design, automation and test in Europe, pp. 1197-1202, 2006, (ISBN 3-9810801-0-6).
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors Proceedings Article
In: DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, 2005.
Operation tables for scheduling in the presence of incomplete bypassing. Proceedings Article
In: CODES+ISSS, pp. 194-199, 2004.