Publications
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level Proceedings Article
In: Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE), 2023.
Report on the 2022 Embedded Systems Week (ESWEEK) Journal Article
In: IEEE Design & Test, vol. 40, iss. 1, pp. 108-111, 2023.
Special Session: Towards an Agile Design Methodology for Efficient, Reliable, and Secure ML Systems Proceedings Article
In: Proceedings of the 2022 IEEE 40th VLSI Test Symposium (VTS), 2022.
Return Data Interleaving for Multi-channel Embedded CMP Systems Journal Article
In: IEEE TVLSI: IEEE Transactions on Very Large Scale Integrated circuits, vol. 20, no. 7, pp. 1351-1354, 2012.
Design of an RNS Reverse Converter for a New Five-Moduli Special Set Proceedings Article
In: pp. 67-70, Proceedings of the great lakes symposium on VLSI, 2012.
Return Data Interleaving for Multi-Channel Embedded CMPs Systems Journal Article
In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, no. 12769237, pp. 1351-1354, 2011.
Improving Application Response Times of Nand Flash based Systems Masters Thesis
School of Computing, Informatics, and Decision Systems Engineering (CIDSE), 2009.
FSAF: File system aware flash translation layer for NAND Flash Memories Proceedings Article
In: Design, Automation Test in Europe Conference Exhibition (DATE), 2009, (ISSN 1530-1591).
Hiding cache miss penalty using priority-based execution for embedded processors Proceedings Article
In: DATE '08: Proceedings of the conference on Design, automation and test in Europe, 2008, (ISBN 978-3-9810801-3-1).
ADL-driven Methodologies for Design Automation of Embedded Processors Book Chapter
In: Processor Description Languages, Chapter 2, pp. 13-33, Elsevier Inc., 2008.
ADL-Driven Methodologies for Design Automation of Programmable Architectures Book Section
In: Processor Description Languages: Applications and Methodologies, 2008.
A compiler-in-the-loop framework to explore horizontally partitioned cache architectures Proceedings Article
In: ASP-DAC '08: Proceedings of the conference on Asia and South Pacific design automation, pp. 328-333, 2008, (ISBN 978-1-4244-1922-7).
Robust Localization in Wireless Sensor Networks through the Revocation of Malicious Anchors Proceedings Article
In: ICC '07. IEEE International Conference on Communications, pp. 3057-3062, 2007.
Compiler Aided Design of Embedded Computers Book Section
In: The Compiler Design Handbook: Optimizations and Machine Code Generation:2nd Edition, 2007.
Automatic Design Space Exploration of Register Bypasses in Embedded Processors Journal Article
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, no. 12, pp. 2102-2115, 2007, (ISSN 0278-0070).
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs Journal Article
In: ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 626-658, 2006, (ISSN 1084-4309).
Retargetable pipeline hazard detection for partially bypassed processors Journal Article
In: vol. 14, pp. 791-801, 2006, (ISBN 1063-8210).
Compiler-in-Loop Exploration of Programmable Embedded Systems PhD Thesis
Donald Bren School of Information and Computer Sciences, 2006.
Compiler-in-the-Loop ADL-driven Early Architectural Exploration Proceedings Article
In: TECHCON 2005: Semiconductor Research Corporation, 2005.
A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor Technical Report
University of California, Irvine 2003.