{"id":108,"date":"2011-02-01T20:07:09","date_gmt":"2011-02-01T20:07:09","guid":{"rendered":"http:\/\/aviral.lab.asu.edu\/?p=108"},"modified":"2020-01-29T17:46:00","modified_gmt":"2020-01-29T17:46:00","slug":"non-coherent-cache-multi-core-processors","status":"publish","type":"post","link":"https:\/\/labs.engineering.asu.edu\/mps-lab\/2011\/02\/non-coherent-cache-multi-core-processors\/","title":{"rendered":"Non-coherent Cache Architecture"},"content":{"rendered":"\n\n\n\n
Limited Local Memory Multi-cores<\/td>\nSoft Error Resilience<\/td>\n<\/tr>\n
Coarse Grain Reconfigurable Arrays<\/td>\nNon-coherent Cache Architecture<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n

Challenge<\/a> Our Approach<\/a> Publications<\/a> Resources<\/a> <\/strong><\/p>\n

<\/a>Challenge<\/strong>
\nOne of the main challenges in scaling the number of cores is scaling the memory architecture. As the number of cores on a chip increases, the design complexity and the power consumption of the cache coherence logic increase exponentially. Therefore, it is inevitable for future multi-core processors to employ non-coherent cache architecture.<\/p>\n

\"\"<\/a>
Intel’s SCC is a research processor which has 48 cores with non-coherent cache memories. (Figure is a courtesy of Intel.)<\/figcaption><\/figure>\n

In non-coherent cache\u00a0\u00a0many-core processors, such as Intel SCC (Single-chip Cloud Computer) shown above, cache coherency must be maintained by software through inter-core communication like message passing. While legacy program source codes are written in shared memory programming model, programmability and scalability are major challenges.\u00a0It is not yet clear if every program can run on such architecture easily \u00a0and efficiently, and if the performance is scalable when the number of cores gets doubled,\u00a0tripled, or even more.<\/p>\n

<\/a>Our Approach<\/strong><\/p>\n

As far as programmability is concerned, virtual shared memory can the best option since all the legacy code can run without any significant transformation. It can be implemented by a library which will invalidate and update the cache lines to maintain coherency.\u00a0However, it may incur a lot of overhead for some applications due to frequent communication. Another option can be automatically transforming message passing style source code from shared memory style source code. The performance of generated code will be affected by various performance considerations and optimizations for the target processor. Careful evaluations and analyses must be done to find the most useful and efficient solution.<\/p>\n

<\/a>Publications<\/strong><\/p>\n

<\/a>Resources<\/strong>\t\t<\/p>\n","protected":false},"excerpt":{"rendered":"

Limited Local Memory Multi-cores Soft Error Resilience Coarse Grain Reconfigurable Arrays Non-coherent Cache Architecture Challenge Our Approach Publications Resources Challenge One of the main challenges in scaling the number of cores is scaling the memory architecture. As the number of cores on a chip increases, the design complexity and the power consumption of the cache…<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"_acf_changed":false,"footnotes":""},"categories":[10],"tags":[],"class_list":["post-108","post","type-post","status-publish","format-standard","hentry","category-news"],"acf":[],"_links":{"self":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/posts\/108","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/comments?post=108"}],"version-history":[{"count":0,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/posts\/108\/revisions"}],"wp:attachment":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/media?parent=108"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/categories?post=108"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/tags?post=108"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}