{"id":4464,"date":"2020-04-24T19:13:15","date_gmt":"2020-04-24T19:13:15","guid":{"rendered":"https:\/\/labs.engineering.asu.edu\/mps-lab\/?page_id=4464"},"modified":"2025-05-28T16:01:34","modified_gmt":"2025-05-28T23:01:34","slug":"software-release","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/mps-lab\/software-release\/","title":{"rendered":"Software Release"},"content":{"rendered":"\n

MLIR<\/a><\/h1>\n\n\n\n
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DSP-MLIR<\/a><\/strong> : Digital Signal Processing Compiler in MLIR<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Error Resilience<\/a><\/h2>\n\n\n\n
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nZDC<\/a><\/strong> : LLVM based compiler for near zero silent data corruption.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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LLVM-r<\/a><\/strong> Resilience-aware LLVM based compiler with instruction-based duplication for error protection.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Expert<\/a><\/strong> Error detection support with redundant multi-threading.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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GemV<\/a><\/strong> Micro-architecture vulnerability estimation tool (based on gem5 simulator).
For a brief summary of error resilience tools, please visit this page<\/a>.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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Machine Learning Accelerators<\/a><\/h1>\n\n\n\n
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dMazeRunner<\/a><\/strong> Dataflow optimization infrastructure for coarse-grain programmable accelerators.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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DiRAC<\/a><\/strong> Architecture template and cycle-level microarchitecture simulator for dataflow accelerators.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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<\/a>Accelerated Computing<\/a><\/h1>\n\n\n\n
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<\/a>CCF<\/a><\/strong> CGRA compilation and simulation framework.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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<\/a>CCF<\/a><\/strong> CGRA compilation and simulation framework.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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<\/a><\/a>Software Managed Manycores<\/a><\/h1>\n\n\n\n
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<\/a><\/a>SMM toolchain<\/a><\/strong> Toolchain for application execution on SMM architectures.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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<\/a><\/a>Cyber-Physical & IoT Systems<\/a><\/h1>\n\n\n\n
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<\/a><\/a>TMA<\/a><\/strong> Timestamp based monitoring tool for CPS applications.<\/p>\n<\/div>\n<\/div>\n\n\n\n

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<\/a><\/a>Jobbed<\/a><\/strong> RTOS for the Raspberry Pi 2B
<\/p>\n<\/div>\n<\/div>\n\n\n\n

<\/p>\n","protected":false},"excerpt":{"rendered":"

MLIR DSP-MLIR : Digital Signal Processing Compiler in MLIR Error Resilience nZDC : LLVM based compiler for near zero silent data corruption. LLVM-r Resilience-aware LLVM based compiler with instruction-based duplication for error protection. Expert Error detection support with redundant multi-threading. GemV Micro-architecture vulnerability estimation tool (based on gem5 simulator).For a brief summary of error resilience…<\/p>\n","protected":false},"author":21,"featured_media":0,"parent":0,"menu_order":12,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-4464","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/4464","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/users\/21"}],"replies":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/comments?post=4464"}],"version-history":[{"count":0,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/4464\/revisions"}],"wp:attachment":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/media?parent=4464"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}