{"id":3918,"date":"2020-01-29T19:08:25","date_gmt":"2020-01-29T19:08:25","guid":{"rendered":"http:\/\/labs.engineering.asu.edu\/cml-lab\/?page_id=3918"},"modified":"2020-06-22T20:54:36","modified_gmt":"2020-06-22T20:54:36","slug":"publications","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/mps-lab\/publications\/","title":{"rendered":"Publications"},"content":{"rendered":"
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245 entries<\/span> «<\/a> ‹<\/a> 1 of 13 ›<\/a> »<\/a> <\/div><\/div>
1.<\/div>

Rishab Kashyap<\/p>

ADAPT: Asymmetric Device Adaptive Parallel Training for Small-Scale Heterogeneous Systems Masters Thesis<\/span> <\/p>

2026<\/span>.<\/p>

BibTeX<\/a><\/span> | Tags: <\/span> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>

@mastersthesis{Kashyap2026THESIS,
\r\ntitle = {ADAPT: Asymmetric Device Adaptive Parallel Training for Small-Scale Heterogeneous Systems},
\r\nauthor = {Rishab Kashyap},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Kashyap2026THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Kashyap2026THESIS.pptx, slides},
\r\nyear  = {2026},
\r\ndate = {2026-02-20},
\r\nurldate = {2026-02-20},
\r\nkeywords = {},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
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2.<\/div>
Sumedh Joshi; Hwisoo So; Aviral Shrivastava\r\n<\/p>
ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors Conference<\/span> <\/p>
 Proceedings of the 2025 International Conference on Hardware\/Software Codesign and System Synthesis, <\/span>2025<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Reliability<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@conference{Joshi2025codes,
\r\ntitle = {ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors},
\r\nauthor = {Sumedh Joshi and Hwisoo So and Aviral Shrivastava
\r\n},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Joshi2025CODES.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Joshi2025CODES.pptx, slides},
\r\nyear  = {2025},
\r\ndate = {2025-10-03},
\r\nurldate = {2025-10-03},
\r\npublisher = { Proceedings of the 2025 International Conference on Hardware\/Software Codesign and System Synthesis},
\r\nkeywords = {Reliability},
\r\npubstate = {published},
\r\ntppubtype = {conference}
\r\n}
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3.<\/div>
Kaustubh Harapanahalli<\/p>
SIGN: A Scalable Incident Detection, Localization, and Severity Estimation using Graph Neural Networks Masters Thesis<\/span> <\/p>
2025<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@mastersthesis{Harapanahalli2025THESIS,
\r\ntitle = {SIGN: A Scalable Incident Detection, Localization, and Severity Estimation using Graph Neural Networks},
\r\nauthor = {Kaustubh Harapanahalli},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Harapanahalli2025THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Harapanahalli2025THESIS.pptx, ppt},
\r\nyear  = {2025},
\r\ndate = {2025-07-07},
\r\nkeywords = {},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
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4.<\/div>
Guna Lagudu; Vinayak Sharma; Aviral Shrivastava<\/p>
LUCI: Lightweight UI Command Interface Proceedings Article<\/span> <\/p>
In: <\/span>Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), <\/span>2025<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span> | Links: <\/span><\/i><\/a><\/i><\/a><\/i><\/a><\/span><\/p>
@inproceedings{Lagudu2025LCTES,
\r\ntitle = {LUCI: Lightweight UI Command Interface},
\r\nauthor = {Guna Lagudu and Vinayak Sharma and Aviral Shrivastava},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Lagudu2025LCTES.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Lagudu2025LCTES.pdf, pdf},
\r\ndoi = {10.1145\/3735452.3735536},
\r\nyear  = {2025},
\r\ndate = {2025-06-16},
\r\nurldate = {2025-06-16},
\r\nbooktitle = {Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)},
\r\nkeywords = {},
\r\npubstate = {published},
\r\ntppubtype = {inproceedings}
\r\n}
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5.<\/div>
Abhinav Kumar; Atharva Khedkar; Hwisoo So; Megan Kuo; Ameya Gurjar; Partha Biswas; Aviral Shrivastava<\/p>
DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing Proceedings Article<\/span> <\/p>
In: <\/span>Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES), <\/span>2025<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span> | Links: <\/span><\/i><\/a><\/i><\/a><\/i><\/a><\/span><\/p>
@inproceedings{Kumar2025LCTES,
\r\ntitle = {DSP-MLIR: A Domain-Specific Language and MLIR Dialect for Digital Signal Processing},
\r\nauthor = {Abhinav Kumar and Atharva Khedkar and Hwisoo So and Megan Kuo and Ameya Gurjar and Partha Biswas and Aviral Shrivastava},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Kumar2025LCTES.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Kumar2025LCTES.pptx, ppt},
\r\ndoi = {10.1145\/3735452.3735527},
\r\nyear  = {2025},
\r\ndate = {2025-06-16},
\r\nurldate = {2025-06-16},
\r\nbooktitle = {Proceedings of Languages, Compilers, Tools and Theory of Embedded Systems (LCTES)},
\r\nkeywords = {},
\r\npubstate = {published},
\r\ntppubtype = {inproceedings}
\r\n}
\r\n<\/pre><\/div>
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6.<\/div>
Mohammad Khayatian; Mohammadreza Mehrabian; Harshith Alamsetti; Aviral Shrivastava\r\n<\/p>
Cooperative Driving of Connected Autonomous Vehicles in Smart Cities using Responsibility-Sensitive Safety Rules Patent<\/span> <\/p>
2025<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Intelligent Transportation Systems<\/a> | Links: <\/span><\/i><\/a><\/span><\/p>
@patent{Khayatian2025Patent,
\r\ntitle = {Cooperative Driving of Connected Autonomous Vehicles in Smart Cities using Responsibility-Sensitive Safety Rules},
\r\nauthor = {Mohammad Khayatian and Mohammadreza Mehrabian and Harshith Alamsetti and Aviral Shrivastava
\r\n},
\r\nurl = {https:\/\/patents.google.com, Google Patents},
\r\nyear  = {2025},
\r\ndate = {2025-03-11},
\r\nurldate = {2025-03-11},
\r\nhowpublished = {https:\/\/patents.google.com\/},
\r\nkeywords = {Intelligent Transportation Systems},
\r\npubstate = {published},
\r\ntppubtype = {patent}
\r\n}
\r\n<\/pre><\/div>
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7.<\/div>
Shreehari Jagadeesha; Edward Andert; Aviral Shrivastava<\/p>
TIPANGLE: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Traffic Cameras on Edge Devices Conference<\/span> <\/p>
IEEE International Conference on Very Large System Integration and Embedded Systems, <\/span>2025<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Best Paper Award<\/a>, Intelligent Transportation Systems<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@conference{Jagadeesha2025VLSISoC,
\r\ntitle = {TIPANGLE: Traffic Tracking at City Scale by Pose Estimation of Pan and Tilt Traffic Cameras on Edge Devices},
\r\nauthor = {Shreehari Jagadeesha and Edward Andert and Aviral Shrivastava},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Jagadeesha2025VLSID.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Jagadeesha2025VLSID.pdf, slides},
\r\nyear  = {2025},
\r\ndate = {2025-01-21},
\r\nurldate = {2025-01-21},
\r\nbooktitle = {IEEE International Conference on Very Large System Integration and Embedded Systems},
\r\njournal = {IEEE International Conference Very Large System Integration and Embedded Systems},
\r\nkeywords = {Best Paper Award, Intelligent Transportation Systems},
\r\npubstate = {published},
\r\ntppubtype = {conference}
\r\n}
\r\n<\/pre><\/div>
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8.<\/div>
Yebon Kim; Jinhyo Jung; Hyunjun Kim; Hwisoo So; Yohan Ko; Aviral Shrivastava; Kyoungwoo Lee; Uiwon Hwang<\/p>
Adversarial Defense on Harmony: Reverse Attack for Robust Models Against Adversarial Attack Journal Article<\/span> <\/p>
In: <\/span>IEEE Access, <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Reliability<\/a> | Links: <\/span><\/i><\/a><\/span><\/p>
@article{Kim2024Access,
\r\ntitle = {Adversarial Defense on Harmony: Reverse Attack for Robust Models Against Adversarial Attack},
\r\nauthor = {Yebon Kim and Jinhyo Jung and Hyunjun Kim and Hwisoo So and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee and Uiwon Hwang},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Hwisoo2024IEEE.pdf, pdf},
\r\nyear  = {2024},
\r\ndate = {2024-11-25},
\r\nurldate = {2024-11-25},
\r\nbooktitle = {IEEE Access},
\r\njournal = {IEEE Access},
\r\nkeywords = {Reliability},
\r\npubstate = {published},
\r\ntppubtype = {article}
\r\n}
\r\n<\/pre><\/div>
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9.<\/div>
Sumedh Joshi<\/p>
ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors Masters Thesis<\/span> <\/p>
2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Reliability<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@mastersthesis{Joshi2025thesis,
\r\ntitle = {ProGIP: Protecting Gradient-based Input Perturbation Approaches for Out-of-distribution Detection From Soft Errors},
\r\nauthor = {Sumedh Joshi},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Joshi2024THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Joshi2024THESIS.pdf, slides},
\r\nyear  = {2024},
\r\ndate = {2024-10-24},
\r\nurldate = {2024-10-24},
\r\nkeywords = {Reliability},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
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10.<\/div>
Francis Mendoza<\/p>
AEGIS: A Special-Purpose Computer Network For Strategic Cyber Defense Masters Thesis<\/span> <\/p>
2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Reliability<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@mastersthesis{mendoza2024thesis,
\r\ntitle = {AEGIS: A Special-Purpose Computer Network For Strategic Cyber Defense},
\r\nauthor = {Francis Mendoza},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Mendoza2024THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Mendoza2024THESIS.pdf, slides},
\r\nyear  = {2024},
\r\ndate = {2024-09-30},
\r\nurldate = {2024-09-30},
\r\nkeywords = {Reliability},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
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11.<\/div>
Aviral Shrivastava; Vinayak Sharma<\/p>
Primer on Data in Quantum Machine Learning Conference<\/span> <\/p>
 2024 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Quantum Machine Learning<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@conference{Shrivastava2024Cases,
\r\ntitle = {Primer on Data in Quantum Machine Learning},
\r\nauthor = {Aviral Shrivastava and Vinayak Sharma},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Shrivastava2024CASES.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Shrivastava2024CASES.pptx, slides},
\r\nyear  = {2024},
\r\ndate = {2024-09-29},
\r\nurldate = {2024-09-29},
\r\nbooktitle = { 2024 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)},
\r\nkeywords = {Quantum Machine Learning},
\r\npubstate = {published},
\r\ntppubtype = {conference}
\r\n}
\r\n<\/pre><\/div>
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12.<\/div>
Abhinav Kumar; Aviral Shrivastava\r\n<\/p>
DSP-MLIR: A Compiler for Digital Signal Processing in MLIR Masters Thesis<\/span> <\/p>
Arizona State University, <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Multi-level Intermediate Representation<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@mastersthesis{Kumar2024thesis,
\r\ntitle = {DSP-MLIR: A Compiler for Digital Signal Processing in MLIR},
\r\nauthor = {Abhinav Kumar and Aviral Shrivastava
\r\n},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Kumar2024THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Kumar2024THESIS.pptx, slides},
\r\nyear  = {2024},
\r\ndate = {2024-09-23},
\r\nurldate = {2024-09-23},
\r\nschool = {Arizona State University},
\r\nkeywords = {Multi-level Intermediate Representation},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
13.<\/div>
Sai Shashank Peddiraju; Kaustubh Harapanahalli; Edward Andert; Aviral Shrivastava<\/p>
IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing Conference<\/span> <\/p>
2024 IEEE 27th International Conference on Intelligent Transportation Systems (ITSC), <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Intelligent Transportation Systems<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@conference{Peddiraju2024ITSC,
\r\ntitle = {IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing},
\r\nauthor = {Sai Shashank Peddiraju and Kaustubh Harapanahalli and Edward Andert and Aviral Shrivastava},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Peddiraju2024ITSC.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/posters\/Peddiraju2024ITSC.pptx, poster},
\r\nyear  = {2024},
\r\ndate = {2024-08-02},
\r\nurldate = {2024-08-02},
\r\nbooktitle = {2024 IEEE 27th International Conference on Intelligent Transportation Systems (ITSC)},
\r\nkeywords = {Intelligent Transportation Systems},
\r\npubstate = {published},
\r\ntppubtype = {conference}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
14.<\/div>
Edward Andert; Francis Mendoza; Hans Behrens; Aviral Shrivastava<\/p>
Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring Conference<\/span> <\/p>
Proceedings of the 61st ACM\/IEEE Design Automation Conference, <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Intelligent Transportation Systems<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@conference{Andert2024dac,
\r\ntitle = {Conclave - Secure and Robust Cooperative Perception for Connected Autonomous Vehicle Using Authenticated Consensus and Trust Scoring},
\r\nauthor = {Edward Andert and Francis Mendoza and Hans Behrens and Aviral Shrivastava},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Andert2024DAC.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Andert2024DAC.pptx, slides},
\r\nyear  = {2024},
\r\ndate = {2024-06-26},
\r\nurldate = {2024-06-26},
\r\npublisher = {Proceedings of the 61st ACM\/IEEE Design Automation Conference},
\r\nkeywords = {Intelligent Transportation Systems},
\r\npubstate = {published},
\r\ntppubtype = {conference}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
15.<\/div>
Jinhyo Jung; Hwisoo So; Woobin Ko; Sumedh Shridhar Joshi; Yebon Kim; Yohan Ko; Aviral Shrivastava; Kyoungwoo Lee<\/p>
Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs Conference<\/span> <\/p>
Proceedings of the 61st ACM\/IEEE Design Automation Conference, <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Reliability<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@conference{Hwisoo2024DAC,
\r\ntitle = {Maintaining Sanity: Algorithm-based Comprehensive Fault Tolerance for CNNs},
\r\nauthor = {Jinhyo Jung and Hwisoo So and Woobin Ko and Sumedh Shridhar Joshi and Yebon Kim and Yohan Ko and Aviral Shrivastava and Kyoungwoo Lee},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Hwisoo2024DAC.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Hwisoo2024DAC.pptx, slides},
\r\nyear  = {2024},
\r\ndate = {2024-06-23},
\r\nurldate = {2024-06-23},
\r\nbooktitle = {Proceedings of the 61st ACM\/IEEE Design Automation Conference},
\r\njournal = {Proceedings of the 61st ACM\/IEEE Design Automation Conference},
\r\nkeywords = {Reliability},
\r\npubstate = {published},
\r\ntppubtype = {conference}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
16.<\/div>
Shail Dave<\/p>
An Agile Methodology for Designing E\ufb03cient Domain-Specific Architectures PhD Thesis<\/span> <\/p>
2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Machine Learning Accelerator Design<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@phdthesis{Dave2024THESIS,
\r\ntitle = {An Agile Methodology for Designing E\ufb03cient Domain-Specific Architectures},
\r\nauthor = {Shail Dave},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Dave2024THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Dave2024THESIS.pptx, slides},
\r\nyear  = {2024},
\r\ndate = {2024-06-10},
\r\nurldate = {2024-06-10},
\r\nkeywords = {Machine Learning Accelerator Design},
\r\npubstate = {published},
\r\ntppubtype = {phdthesis}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
17.<\/div>
Sai Shashank Peddiraju<\/p>
IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing Masters Thesis<\/span> <\/p>
2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Intelligent Transportation Systems<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@mastersthesis{Peddiraju2024Thesis,
\r\ntitle = {IncidentNet: Traffic Incident Detection, Localization and Severity Estimation with Sparse Sensing},
\r\nauthor = {Sai Shashank Peddiraju},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Peddiraju2024THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Peddiraju2024THESIS.pptx, ppt},
\r\nyear  = {2024},
\r\ndate = {2024-05-14},
\r\nurldate = {2024-05-14},
\r\nkeywords = {Intelligent Transportation Systems},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
18.<\/div>
Shail Dave; Aviral Shrivastava; Tony Nowatzki<\/p>
Systems and methods for agile and explainable optimization of efficient hardware\/software codesigns for domain-specific computing systems using bottleneck analysis Patent<\/span> <\/p>
2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>Machine Learning Accelerator Design<\/a> | Links: <\/span><\/i><\/a><\/span><\/p>
@patent{Dave2024Patent,
\r\ntitle = {Systems and methods for agile and explainable optimization of efficient hardware\/software codesigns for domain-specific computing systems using bottleneck analysis},
\r\nauthor = {Shail Dave and Aviral Shrivastava and Tony Nowatzki},
\r\nurl = {https:\/\/patents.google.com\/patent\/US20240134769A1\/en, Google Patents},
\r\nyear  = {2024},
\r\ndate = {2024-04-25},
\r\nurldate = {2024-04-25},
\r\nhowpublished = {https:\/\/patents.google.com\/patent\/US20240134769A1\/en},
\r\nkeywords = {Machine Learning Accelerator Design},
\r\npubstate = {published},
\r\ntppubtype = {patent}
\r\n}
\r\n<\/pre><\/div>
Close<\/a><\/p><\/div><\/div><\/div>
19.<\/div>
Guna Lagudu<\/p>
LUCI: Multi-Application Orchestration Agent Masters Thesis<\/span> <\/p>
Arizona State University, <\/span>2024<\/span>.<\/p>
BibTeX<\/a><\/span> | Tags: <\/span>LLM Applications<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/span><\/p>
@mastersthesis{Lagudu2024Thesis,
\r\ntitle = {LUCI: Multi-Application Orchestration Agent},
\r\nauthor = {Guna Lagudu},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Lagudu2024THESIS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Lagudu2024THESIS.pptx, slides},
\r\nyear  = {2024},
\r\ndate = {2024-04-08},
\r\nurldate = {2024-04-08},
\r\nschool = {Arizona State University},
\r\nkeywords = {LLM Applications},
\r\npubstate = {published},
\r\ntppubtype = {mastersthesis}
\r\n}
\r\n<\/pre><\/div>
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20.<\/div>
Shail Dave; Tony Nowatzki; Aviral Shrivastava<\/p>
Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware\/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis Proceedings Article<\/span> <\/p>
In: <\/span>Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), <\/span>2024<\/span>, (Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED))<\/span>.<\/p>
Abstract<\/a><\/span> | BibTeX<\/a><\/span> | Tags: <\/span>Machine Learning Accelerator Design<\/a> | Links: <\/span><\/i><\/a><\/i><\/a><\/i><\/a><\/i><\/a><\/span><\/p>
@inproceedings{Dave2024ASPLOS,
\r\ntitle = {Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware\/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis},
\r\nauthor = {Shail Dave and Tony Nowatzki and Aviral Shrivastava},
\r\nurl = {https:\/\/mpslab-asu.github.io\/publications\/papers\/Dave2024ASPLOS.pdf, pdf
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/slides\/Dave2024ASPLOS.pptx, slides
\r\nhttps:\/\/mpslab-asu.github.io\/publications\/posters\/Dave2024ASPLOS.pdf, poster
\r\nhttps:\/\/youtu.be\/y-F1Cp66_oQ, teaser},
\r\nyear  = {2024},
\r\ndate = {2024-04-02},
\r\nurldate = {2024-04-02},
\r\nbooktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)},
\r\nabstract = {Effective design space exploration (DSE) is paramount for hardware\/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE \u2013 a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an
\r\nAPI for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6\u00d7 lower latency in 47\u00d7 fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.},
\r\nnote = {Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)},
\r\nkeywords = {Machine Learning Accelerator Design},
\r\npubstate = {published},
\r\ntppubtype = {inproceedings}
\r\n}
\r\n<\/pre><\/div>
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Effective design space exploration (DSE) is paramount for hardware\/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE \u2013 a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an
\r\nAPI for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6\u00d7 lower latency in 47\u00d7 fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.<\/div>
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