{"id":2845,"date":"2017-02-17T17:40:21","date_gmt":"2017-02-18T00:40:21","guid":{"rendered":"http:\/\/aviral.lab.asu.edu\/?page_id=2845"},"modified":"2020-08-23T03:35:59","modified_gmt":"2020-08-23T03:35:59","slug":"ptv","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/mps-lab\/low-power-computing\/ptv\/","title":{"rendered":"Power, Temperature and Variation aware Computing"},"content":{"rendered":"

Challenge<\/h3>\r\n

Power consumption, process variations, and temperature are all problems due to technology scaling to incredible levels. Our approach to deal with power, temperature and process variations is to expose them to microarchitecture and software levels, where instruction scheduling and component sleep solutions can be developed to handle these issues.<\/p>\r\n

Challenge of Power, Temperature, and Variations<\/h3>\r\n

\"\"<\/p>\r\n

Two important consequences of technology scaling are\u00a0the increase in leakage power\u00a0and increase in variation in the characteristics of manufactured devices. Leakage power is projected to contribute more than 40% of total power budget in processors fabricated in 65 nm technology and beyond. Unlike dynamic power, leakage power is highly sensitive to variations in gate dimensions as well as the operational temperature. High variation in the power consumption results in the\u00a0significant overestimation of the specification, leading to increased design time\/effort and results in significant loss of parameterized yield. Hence, reducing the total power, temperature and the variation in the power consumption is an important problem.<\/p>\r\n

Leakage-Aware Power Gating<\/h3>\r\n

\"\"<\/p>\r\n

We introduce a leakage sensor in FUs, and develop a temperature and process variations aware power gating technique. Our power gating approach is based on the IPC, using which it determines how many FUs must be on. Once this is decided, based on the leakage of the FUs (which automatically takes temperature into account), which FUs should be power gates is determined.<\/p>\r\n

Relevant Publications<\/a><\/h3>\r\n\r\n

 <\/p>\r\n","protected":false},"excerpt":{"rendered":"

Challenge Power consumption, process variations, and temperature are all problems due to technology scaling to incredible levels. Our approach to deal with power, temperature and process variations is to expose them to microarchitecture and software levels, where instruction scheduling and component sleep solutions can be developed to handle these issues. Challenge of Power, Temperature, and…<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":2795,"menu_order":45,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-2845","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/2845","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/comments?post=2845"}],"version-history":[{"count":0,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/2845\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/2795"}],"wp:attachment":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/media?parent=2845"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}