{"id":2795,"date":"2017-02-11T19:56:28","date_gmt":"2017-02-12T02:56:28","guid":{"rendered":"http:\/\/aviral.lab.asu.edu\/?page_id=2795"},"modified":"2020-08-23T05:15:40","modified_gmt":"2020-08-23T05:15:40","slug":"low-power-computing","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/mps-lab\/low-power-computing\/","title":{"rendered":"Low-Power Computing"},"content":{"rendered":"\r\n<h3 class=\"has-text-align-center wp-block-heading\"><strong>[PICA] Processor Idle Cycle Aggregation<\/strong><\/h3>\r\n\r\n<div class=\"wp-block-image\">\r\n<figure class=\"aligncenter size-large is-resized\"><a href=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/pica\/\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-416\" src=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/aggregation-execution.png\" alt=\"\" width=\"503\" height=\"217\" srcset=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/aggregation-execution.png 651w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/aggregation-execution-300x129.png 300w\" sizes=\"auto, (max-width: 503px) 100vw, 503px\" \/><\/a><\/figure>\r\n<\/div>\r\n\r\n<h3 class=\"has-text-align-center wp-block-heading\"><strong>[SBH] Software Branch Hinting<\/strong><\/h3>\r\n\r\n<div class=\"wp-block-image\">\r\n<figure class=\"aligncenter size-large is-resized\"><a href=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/sbh\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-601\" src=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/cellArch.png\" alt=\"\" width=\"542\" height=\"325\" srcset=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/cellArch.png 1000w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/cellArch-300x180.png 300w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/cellArch-768x461.png 768w\" sizes=\"auto, (max-width: 542px) 100vw, 542px\" \/><\/a><\/figure>\r\n<\/div>\r\n\r\n<h3 class=\"has-text-align-center wp-block-heading\"><strong>[PTV] Power, Temperature and Variation aware Computing<\/strong><\/h3>\r\n\r\n<div class=\"wp-block-image\">\r\n<figure class=\"aligncenter size-large is-resized\"><a href=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/ptv\/\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-424\" src=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/lapg.png\" alt=\"\" width=\"479\" height=\"202\" srcset=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/lapg.png 865w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/lapg-300x127.png 300w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/lapg-768x324.png 768w\" sizes=\"auto, (max-width: 479px) 100vw, 479px\" \/><\/a><\/figure>\r\n<\/div>\r\n\r\n<h3 class=\"has-text-align-center wp-block-heading\"><strong>[rISA] Reduced bit-width Instruction Set Architecture<\/strong><\/h3>\r\n\r\n<div class=\"wp-block-image\">\r\n<figure class=\"aligncenter size-large is-resized\"><a href=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/risa\/\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-384\" src=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/dualISA.png\" alt=\"\" width=\"511\" height=\"154\" srcset=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/dualISA.png 475w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/dualISA-300x90.png 300w\" sizes=\"auto, (max-width: 511px) 100vw, 511px\" \/><\/a><\/figure>\r\n<\/div>\r\n\r\n<h3 class=\"has-text-align-center wp-block-heading\"><strong>[BAC] Bypass Aware Compiler<\/strong><\/h3>\r\n\r\n<div class=\"wp-block-image\">\r\n<figure class=\"aligncenter size-large is-resized\"><a href=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/bac\/\"><img loading=\"lazy\" decoding=\"async\" class=\"wp-image-394\" src=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/partial-bypassing.png\" alt=\"\" width=\"467\" height=\"172\" srcset=\"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/partial-bypassing.png 410w, https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-content\/uploads\/sites\/8\/2011\/06\/partial-bypassing-300x110.png 300w\" sizes=\"auto, (max-width: 467px) 100vw, 467px\" \/><\/a><\/figure>\r\n<\/div>\r\n","protected":false},"excerpt":{"rendered":"<p class=\"mb-2\">[PICA] Processor Idle Cycle Aggregation [SBH] Software Branch Hinting [PTV] Power, Temperature and Variation aware Computing [rISA] Reduced bit-width Instruction Set Architecture [BAC] Bypass Aware Compiler<\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":43,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-2795","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/2795","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/comments?post=2795"}],"version-history":[{"count":0,"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/pages\/2795\/revisions"}],"wp:attachment":[{"href":"https:\/\/labs.engineering.asu.edu\/mps-lab\/wp-json\/wp\/v2\/media?parent=2795"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}