Publications
21.
Shail Dave; Tony Nowatzki; Aviral Shrivastava
Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis Proceedings Article
In: Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), 2024, (Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)).
Abstract | BibTeX | Tags: Machine Learning Accelerator Design | Links:
@inproceedings{Dave2024ASPLOS,
title = {Explainable-DSE: An Agile and Explainable Exploration of Efficient Hardware/Software Codesigns of Deep Learning Accelerators Using Bottleneck Analysis},
author = {Shail Dave and Tony Nowatzki and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Dave2024ASPLOS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Dave2024ASPLOS.pptx, slides
https://mpslab-asu.github.io/publications/posters/Dave2024ASPLOS.pdf, poster
https://youtu.be/y-F1Cp66_oQ, teaser},
year = {2024},
date = {2024-04-02},
urldate = {2024-04-02},
booktitle = {Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS)},
abstract = {Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE – a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an
API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.},
note = {Won Silver Medal at ACM Student Research Competition 2022-23 (Host: ACM SIGBED)},
keywords = {Machine Learning Accelerator Design},
pubstate = {published},
tppubtype = {inproceedings}
}
Effective design space exploration (DSE) is paramount for hardware/software codesigns of deep learning accelerators that must meet strict execution constraints. For their vast search space, existing DSE techniques can require excessive number of trials to obtain valid and efficient solution because they rely on black-box explorations that do not reason about design inefficiencies. In this paper, we propose Explainable-DSE – a framework for DSE of DNN accelerator codesigns using bottleneck analysis. By leveraging information about execution costs from bottleneck models, our DSE is able to identify the bottlenecks and therefore the reasons for design inefficiency, and can therefore make mitigating acquisitions in further explorations. We describe the construction of such bottleneck models for DNN accelerator domain. We also propose an
API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.
API for expressing such domain-specific models and integrating them into the DSE framework. Acquisitions of our DSE framework caters to multiple bottlenecks in executions of workloads like DNNs that contain different functions with diverse execution characteristics. Evaluations for recent computer vision and language models show that Explainable-DSE mostly explores effectual candidates, achieving codesigns of 6× lower latency in 47× fewer iterations vs. non-explainable techniques using evolutionary or ML-based optimizations. By taking minutes or tens of iterations, it enables opportunities for runtime DSEs.
22.
Mahesh Balasubramanian; Aviral Shrivastava
Systems and methods for fast-mapping of coarse-grained reconfigurable arrays Patent
2024.
BibTeX | Tags: Coarse-Grained Reconfigurable Arrays | Links:
@patent{balasubramanian2024patent,
title = {Systems and methods for fast-mapping of coarse-grained reconfigurable arrays},
author = {Mahesh Balasubramanian and Aviral Shrivastava},
url = {https://patents.google.com/patent/US20240311230A1/en, Google Patents},
year = {2024},
date = {2024-03-13},
urldate = {2024-03-13},
howpublished = {https://patents.google.com/patent/US20240311230A1/en},
keywords = {Coarse-Grained Reconfigurable Arrays},
pubstate = {published},
tppubtype = {patent}
}
23.
Mahesh Balasubramanian; Aviral Shrivastava
Systems and methods for improved mapping of computational loops on reconfigurable architectures Patent
2024.
BibTeX | Tags: Coarse-Grained Reconfigurable Arrays | Links:
@patent{balasubramanian2024patent,
title = {Systems and methods for improved mapping of computational loops on reconfigurable architectures},
author = {Mahesh Balasubramanian and Aviral Shrivastava},
url = {https://patents.google.com/patent/US11928468B2/en, Google Patents},
year = {2024},
date = {2024-03-12},
urldate = {2024-03-12},
howpublished = {https://patents.google.com/patent/US11928468B2/en},
keywords = {Coarse-Grained Reconfigurable Arrays},
pubstate = {published},
tppubtype = {patent}
}
24.
Aviral Shrivastava; Mohammad Khayatian; Bob Iannucci
Design Methodology for Robust, Distributed Time-Sensitive Applications Journal Article
In: IEEE Internet of Things Magazine, 2024.
BibTeX | Tags: Real-Time Systems, Reliability | Links:
@article{shrivastava2024IoTM,
title = {Design Methodology for Robust, Distributed Time-Sensitive Applications},
author = {Aviral Shrivastava and Mohammad Khayatian and Bob Iannucci},
url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2024IEEE.pdf, pdf},
year = {2024},
date = {2024-01-11},
urldate = {2024-01-11},
journal = {IEEE Internet of Things Magazine},
keywords = {Real-Time Systems, Reliability},
pubstate = {published},
tppubtype = {article}
}
25.
Benjamin Willis; Aviral Shrivastava; Joshua Mack; Shail Dave; Chaitali Chakrabarti; John Brunhaver
Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs Journal Article
In: IEEE Transactions on Computers, 2024.
BibTeX | Tags: | Links:
@article{Willis2024TC,
title = {Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs},
author = {Benjamin Willis and Aviral Shrivastava and Joshua Mack and Shail Dave and Chaitali Chakrabarti and John Brunhaver},
url = {https://mpslab-asu.github.io/publications/papers/Willis2024TC.pdf, pdf},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-01},
journal = {IEEE Transactions on Computers},
keywords = {},
pubstate = {published},
tppubtype = {article}
}
26.
Mohammad Khayatian; Mohammadreza Mehrabian; I-Ching Tseng; Chung-Wei Lin; Calin Belta; Aviral Shrivastava
Cooperative Driving of Connected Autonomous Vehicles using Responsibility Sensitive Safety Rules: A Control Barrier Functions Approach Journal Article
In: IEEE Transactions on Cyber Physical Systems, vol. 8, iss. 1, 2024.
BibTeX | Tags: Intelligent Transportation Systems | Links:
@article{Khayatian2024TCPS,
title = {Cooperative Driving of Connected Autonomous Vehicles using Responsibility Sensitive Safety Rules: A Control Barrier Functions Approach},
author = {Mohammad Khayatian and Mohammadreza Mehrabian and I-Ching Tseng and Chung-Wei Lin and Calin Belta and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Khayatian2024TCPS.pdf, pdf},
year = {2024},
date = {2024-01-01},
urldate = {2024-01-01},
journal = {IEEE Transactions on Cyber Physical Systems},
volume = {8},
issue = {1},
keywords = {Intelligent Transportation Systems},
pubstate = {published},
tppubtype = {article}
}
27.
Vinayak Sharma; Aviral Shrivastava
Quantum Polar Metric Learning: Efficient Classically Learned Quantum Embeddings Working paper
ArXiV, 2023.
Abstract | BibTeX | Tags: Quantum Machine Learning | Links:
@workingpaper{sharma2023quantum,
title = {Quantum Polar Metric Learning: Efficient Classically Learned Quantum Embeddings},
author = {Vinayak Sharma and Aviral Shrivastava },
url = {https://mpslab-asu.github.io/publications/papers/Sharma2023Arxiv.pdf, pdf
https://mpslab-asu.github.io/QPMeL/},
doi = { https://doi.org/10.48550/arXiv.2312.01655},
year = {2023},
date = {2023-12-04},
urldate = {2023-12-04},
abstract = {Deep metric learning has recently shown extremely promising results in the classical data domain, creating well-separated feature spaces. This idea was also adapted to quantum computers via Quantum Metric Learning(QMeL). QMeL consists of a 2 step process with a classical model to compress the data to fit into the limited number of qubits, then train a Parameterized Quantum Circuit(PQC) to create better separation in Hilbert Space. However, on Noisy Intermediate Scale Quantum (NISQ) devices. QMeL solutions result in high circuit width and depth, both of which limit scalability. We propose Quantum Polar Metric Learning (QPMeL) that uses a classical model to learn the parameters of the polar form of a qubit. We then utilize a shallow PQC with Ry and Rz gates to create the state and a trainable layer of ZZ(θ)-gates to learn entanglement. The circuit also computes fidelity via a SWAP Test for our proposed Fidelity Triplet Loss function, used to train both classical and quantum components. When compared to QMeL approaches, QPMeL achieves 3X better multi-class separation, while using only 1/2 the number of gates and depth. We also demonstrate that QPMeL outperforms classical networks with similar configurations, presenting a promising avenue for future research on fully classical models with quantum loss functions.},
howpublished = {ArXiV},
keywords = {Quantum Machine Learning},
pubstate = {published},
tppubtype = {workingpaper}
}
Deep metric learning has recently shown extremely promising results in the classical data domain, creating well-separated feature spaces. This idea was also adapted to quantum computers via Quantum Metric Learning(QMeL). QMeL consists of a 2 step process with a classical model to compress the data to fit into the limited number of qubits, then train a Parameterized Quantum Circuit(PQC) to create better separation in Hilbert Space. However, on Noisy Intermediate Scale Quantum (NISQ) devices. QMeL solutions result in high circuit width and depth, both of which limit scalability. We propose Quantum Polar Metric Learning (QPMeL) that uses a classical model to learn the parameters of the polar form of a qubit. We then utilize a shallow PQC with Ry and Rz gates to create the state and a trainable layer of ZZ(θ)-gates to learn entanglement. The circuit also computes fidelity via a SWAP Test for our proposed Fidelity Triplet Loss function, used to train both classical and quantum components. When compared to QMeL approaches, QPMeL achieves 3X better multi-class separation, while using only 1/2 the number of gates and depth. We also demonstrate that QPMeL outperforms classical networks with similar configurations, presenting a promising avenue for future research on fully classical models with quantum loss functions.
28.
Shreehari Jagadeesha
TIPANGLE: A Machine Learning Approach for Accurate Spatial Pan and Tilt Angle Determination of Pan Tilt Traffic Cameras Masters Thesis
Arizona State University, 2023.
BibTeX | Tags: Intelligent Transportation Systems | Links:
@mastersthesis{Jagadeesha2023THESIS,
title = {TIPANGLE: A Machine Learning Approach for Accurate Spatial Pan and Tilt Angle Determination of Pan Tilt Traffic Cameras},
author = {Shreehari Jagadeesha},
url = {https://mpslab-asu.github.io/publications/papers/Jagadeesha2023THESIS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Jagadeesha2023THESIS.pptx, slides},
year = {2023},
date = {2023-11-10},
urldate = {2023-11-10},
school = {Arizona State University},
keywords = {Intelligent Transportation Systems},
pubstate = {published},
tppubtype = {mastersthesis}
}
29.
Hwisoo So; Yohan Ko; Jinhyo Jung; Kyoungwoo Lee; Aviral Shrivastava
gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration Journal Article
In: Electronics 2023, 12(22), 4573, 2023.
BibTeX | Tags: Reliability | Links:
@article{so2023electronics,
title = {gemV-tool: A Comprehensive Soft Error Reliability Estimation Tool for Design Space Exploration},
author = {Hwisoo So and Yohan Ko and Jinhyo Jung and Kyoungwoo Lee and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Hwisoo2023Electronics.pdf, pdf},
year = {2023},
date = {2023-11-08},
urldate = {2023-11-08},
journal = {Electronics 2023, 12(22), 4573},
keywords = {Reliability},
pubstate = {published},
tppubtype = {article}
}
30.
Shail Dave; Aviral Shrivastava
Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures Conference
Proceedings of the TECHCON, 2023.
Abstract | BibTeX | Tags: Machine Learning Accelerator Design | Links:
@conference{Dave2023TECHCON,
title = {Automating the Architectural Execution Modeling and Characterization of Domain-Specific Architectures},
author = {Shail Dave and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Dave2023TECHCON.pdf, pdf
https://mpslab-asu.github.io/publications/posters/Dave2023TECHCON.pptx, poster},
year = {2023},
date = {2023-09-11},
urldate = {2023-09-11},
booktitle = {Proceedings of the TECHCON},
abstract = {Domain-specific architectures (DSAs) are increasingly designed to efficiently process a variety of workloads, such as deep learning, linear algebra, and graph analytics. Most research efforts have focused on proposing new DSAs or efficiently exploring hardware/software designs of previously proposed architecture templates. Recent architectural modeling or simulation frameworks for DSAs can analyze execution costs, e.g., for a limited architectural templates for dense DNNs such as systolic arrays or a spatial architecture with an array of processing elements and 3-level memory hierarchy. However, they are manually developed by domain-experts, containing several 1000s of lines-of-code, and extending them for characterizing new architectures is infeasible, such as DSAs for sparse DNNs. Further, the lack of automated architecture-level execution modeling limits the design space of novel architectures that can be explored/optimized, affecting overall efficiency of solutions, and it delays time-to-market with low sustainability of design process.
To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.},
keywords = {Machine Learning Accelerator Design},
pubstate = {published},
tppubtype = {conference}
}
Domain-specific architectures (DSAs) are increasingly designed to efficiently process a variety of workloads, such as deep learning, linear algebra, and graph analytics. Most research efforts have focused on proposing new DSAs or efficiently exploring hardware/software designs of previously proposed architecture templates. Recent architectural modeling or simulation frameworks for DSAs can analyze execution costs, e.g., for a limited architectural templates for dense DNNs such as systolic arrays or a spatial architecture with an array of processing elements and 3-level memory hierarchy. However, they are manually developed by domain-experts, containing several 1000s of lines-of-code, and extending them for characterizing new architectures is infeasible, such as DSAs for sparse DNNs. Further, the lack of automated architecture-level execution modeling limits the design space of novel architectures that can be explored/optimized, affecting overall efficiency of solutions, and it delays time-to-market with low sustainability of design process.
To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.
To address this issue, this paper introduces DSAProf : a framework for automated execution modeling and bottleneck characterization by a modular, dataflow-driven approach. The framework uses a flow-graph-based methodology for modeling DSAs in a modular manner via a library of architectural components and analyzing their executions. The methodology can account for analytically modeling and simulating intricacies in the presence of a variety of architectural features such as asynchronous execution of workgroups, sparse data processing, arbitrary buffer hierarchies, and multi-chip or mixed-precision modules. Preliminary evaluations of modeling previously proposed DSAs for dense/sparse deep learning demonstrate that our approach is extensible for novel DSAs and it can accurately and automatically characterize their latency and identify execution bottlenecks, without requiring designers to manually build analysis/simulator from scratch for every DSA.
31.
Matthew Szeto; Edward Andert; Aviral Shrivastava; Martin Reisslein; Chung Wei Lin; Christ Richmond
B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles Journal Article
In: ACM Transactions on Embedded Computing Systems, vol. 22, iss. 5, no. 154, pp. 1-23, 2023.
BibTeX | Tags: Intelligent Transportation Systems | Links:
@article{Szeto2023TECS,
title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles},
author = {Matthew Szeto and Edward Andert and Aviral Shrivastava and Martin Reisslein and Chung Wei Lin and Christ Richmond},
url = {https://mpslab-asu.github.io/publications/papers/Szeto2023TECS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides},
year = {2023},
date = {2023-09-09},
urldate = {2023-09-09},
journal = {ACM Transactions on Embedded Computing Systems},
volume = {22},
number = {154},
issue = {5},
pages = {1-23},
keywords = {Intelligent Transportation Systems},
pubstate = {published},
tppubtype = {article}
}
32.
Mohammadreza Mehrabian; Mohammad Khayatian; Aviral Shrivastava; Patricia Derler; Hugo Andrade
A run-time verification method with consideration of uncertainties for cyber-physical systems Journal Article
In: Microprocessors and Microsystems, vol. 101, 2023.
BibTeX | Tags: Cyber Physical and IoT Systems | Links:
@article{Mehrabian2023MICPRO,
title = {A run-time verification method with consideration of uncertainties for cyber-physical systems},
author = {Mohammadreza Mehrabian and Mohammad Khayatian and Aviral Shrivastava and Patricia Derler and Hugo Andrade},
url = {https://mpslab-asu.github.io/publications/papers/Mehrabian2023MICPRO.pdf, pdf},
year = {2023},
date = {2023-06-22},
urldate = {2023-06-22},
journal = {Microprocessors and Microsystems},
volume = {101},
keywords = {Cyber Physical and IoT Systems},
pubstate = {published},
tppubtype = {article}
}
33.
Yi Hu; Chaoran Zhang; Edward Andert; Harshul Singh; Aviral Shrivastava; James Laudon; Yanqi Zhou; Bob Iannucci; Carlee Joe-Wong
GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing Proceedings Article
In: Proceedings of the Sixth Conference on Machine Learning and Systems (MLSys), 2023.
BibTeX | Tags: Machine Learning Accelerator Design, Real-Time Systems | Links:
@inproceedings{Hu2023MLSYS,
title = {GiPH: Generalizable Placement Learning for Adaptive Heterogeneous Computing},
author = {Yi Hu and Chaoran Zhang and Edward Andert and Harshul Singh and Aviral Shrivastava and James Laudon and Yanqi Zhou and Bob Iannucci and Carlee Joe-Wong},
url = {https://mpslab-asu.github.io/publications/papers/Hu2023MLSYS.pdf, pdf},
year = {2023},
date = {2023-06-04},
urldate = {2023-06-04},
booktitle = {Proceedings of the Sixth Conference on Machine Learning and Systems (MLSys)},
keywords = {Machine Learning Accelerator Design, Real-Time Systems},
pubstate = {published},
tppubtype = {inproceedings}
}
34.
Matthew Szeto
B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles Masters Thesis
Arizona State University, 2023.
BibTeX | Tags: Intelligent Transportation Systems, Intelligent Transportation Systems | Links:
@mastersthesis{Szeto2023THESIS,
title = {B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles},
author = {Matthew Szeto},
url = {https://mpslab-asu.github.io/publications/papers/Szeto2023THESIS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Szeto2023THESIS.pptx, slides},
year = {2023},
date = {2023-05-08},
urldate = {2023-05-08},
school = {Arizona State University},
keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems},
pubstate = {published},
tppubtype = {mastersthesis}
}
35.
Behnaz Ranjbar; Florian Klemme; Paul R. Genssler; Hussam Amrouch; Jinhyo Jung; Shail Dave; Hwisoo So; Kyongwoo Lee; Aviral Shrivastava; Ji-Yung Lin; Pieter Weckx; Subrat Mishra; Francky Catthoor; Dwaipayan Biswas; Akash Kumar
Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level Proceedings Article
In: Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE), 2023.
BibTeX | Tags: Efficient Embedded Computing, Machine Learning Accelerator Design, Reliability | Links:
@inproceedings{Ranjbar2023DATE,
title = {Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application Level},
author = {Behnaz Ranjbar and Florian Klemme and Paul R. Genssler and Hussam Amrouch and Jinhyo Jung and Shail Dave and Hwisoo So and Kyongwoo Lee and Aviral Shrivastava and Ji-Yung Lin and Pieter Weckx and Subrat Mishra and Francky Catthoor and Dwaipayan Biswas and Akash Kumar},
url = {https://mpslab-asu.github.io/publications/papers/Ranjbar2023DATE.pdf, paper
https://mpslab-asu.github.io/publications/slides/Ranjbar2023DATE.pptx, slides},
year = {2023},
date = {2023-04-17},
urldate = {2023-04-17},
booktitle = {Proceedings of the 26th International Conference on Design Automation and Test in Europe (DATE)},
keywords = {Efficient Embedded Computing, Machine Learning Accelerator Design, Reliability},
pubstate = {published},
tppubtype = {inproceedings}
}
36.
Sanggu Park; Edward Andert; Aviral Shrivastava
Blame-Free Motion Planning in Hybrid Traffic Journal Article
In: IEEE Transactions on Intelligent Vehicles, pp. 1-10, 2023.
BibTeX | Tags: Intelligent Transportation Systems, Intelligent Transportation Systems | Links:
@article{ParkTIV2023,
title = {Blame-Free Motion Planning in Hybrid Traffic},
author = {Sanggu Park and Edward Andert and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Park2023TIV.pdf, paper},
year = {2023},
date = {2023-04-05},
urldate = {2023-04-05},
journal = {IEEE Transactions on Intelligent Vehicles},
pages = {1-10},
keywords = {Intelligent Transportation Systems, Intelligent Transportation Systems},
pubstate = {published},
tppubtype = {article}
}
37.
Moslem Didehban; Hwisoo So; Prudhvi Gali; Aviral Shrivastava; Kyoungwoo Lee
Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication Journal Article
In: IEEE Transactions on Dependable and Secure Computing, vol. 1, pp. 1-16, 2023.
Abstract | BibTeX | Tags: Reliability | Links:
@article{Didehban2023TDSC,
title = {Generic Soft Error Data and Control Flow Error Detection by Instruction Duplication},
author = {Moslem Didehban and Hwisoo So and Prudhvi Gali and Aviral Shrivastava and Kyoungwoo Lee},
url = {https://mpslab-asu.github.io/publications/papers/Didehban2023TDSC.pdf, paper},
year = {2023},
date = {2023-02-14},
urldate = {2023-02-14},
journal = {IEEE Transactions on Dependable and Secure Computing},
volume = {1},
pages = {1-16},
abstract = {Transient faults or soft errors are considered one of the most daunting reliability challenges for microprocessors. Software solutions for soft error protection are attractive because they can provide flexible and effective error protection. For instance, nZDC [1] state-of-the-art instruction duplication error protection scheme achieves a high degree of error detection by verifying the results of memory write operations and utilizes an effective control-flow checking mechanism. However, nZDC control-flow checking mechanism is architecture-dependent and suffers from some vulnerability holes. In this work, we address these issues by substituting nZDC control-flow checking mechanism with a general (ISA-independent) scheme and propose two transformations, coarse-grained scheduling, and asymmetric control-flow signatures, for hard-to-detect control flow errors. Fault injection experiments on different hardware components of synthesizable Verilog description of an OpenRISC-based microprocessor reveal that the proposed transformation shows 85% less silent data corruptions compared to nZDC. In addition, programs protected by the proposed scheme run on average around 37% faster than nZDC-protected programs.},
keywords = {Reliability},
pubstate = {published},
tppubtype = {article}
}
Transient faults or soft errors are considered one of the most daunting reliability challenges for microprocessors. Software solutions for soft error protection are attractive because they can provide flexible and effective error protection. For instance, nZDC [1] state-of-the-art instruction duplication error protection scheme achieves a high degree of error detection by verifying the results of memory write operations and utilizes an effective control-flow checking mechanism. However, nZDC control-flow checking mechanism is architecture-dependent and suffers from some vulnerability holes. In this work, we address these issues by substituting nZDC control-flow checking mechanism with a general (ISA-independent) scheme and propose two transformations, coarse-grained scheduling, and asymmetric control-flow signatures, for hard-to-detect control flow errors. Fault injection experiments on different hardware components of synthesizable Verilog description of an OpenRISC-based microprocessor reveal that the proposed transformation shows 85% less silent data corruptions compared to nZDC. In addition, programs protected by the proposed scheme run on average around 37% faster than nZDC-protected programs.
38.
Aviral Shrivastava; Xiaobo Sharon Hu
Report on the 2022 Embedded Systems Week (ESWEEK) Journal Article
In: IEEE Design & Test, vol. 40, iss. 1, pp. 108-111, 2023.
Abstract | BibTeX | Tags: Cyber Physical and IoT Systems, Efficient Embedded Computing, Machine Learning Accelerator Design, Real-Time Systems, Reliability | Links:
@article{Shrivastava2023D&T,
title = {Report on the 2022 Embedded Systems Week (ESWEEK)},
author = {Aviral Shrivastava and Xiaobo Sharon Hu},
url = {https://mpslab-asu.github.io/publications/papers/Shrivastava2023D&T.pdf, pdf},
year = {2023},
date = {2023-01-23},
urldate = {2023-01-23},
journal = {IEEE Design & Test},
volume = {40},
issue = {1},
pages = {108-111},
abstract = {Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES); the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS); and the International Conference on Embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.},
keywords = {Cyber Physical and IoT Systems, Efficient Embedded Computing, Machine Learning Accelerator Design, Real-Time Systems, Reliability},
pubstate = {published},
tppubtype = {article}
}
Embedded Systems Week (ESWEEK) is the premier event covering all aspects of hardware and software design for intelligent and connected computing systems. By bringing together three leading conferences [the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES); the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS); and the International Conference on Embedded Software (EMSOFT)] and a variety of symposia, hot-topic workshops, tutorials, and education classes, ESWEEK presents to the attendees a wide range of topics unveiling state-of-the-art embedded software, embedded architectures, and embedded system designs.
39.
Quoc Long Vinh Ta
COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops Masters Thesis
Arizona State University, 2022.
BibTeX | Tags: Coarse-Grained Reconfigurable Arrays | Links:
@mastersthesis{Ta2022THESIS,
title = {COMSAT: Modified Modulo Scheduling Techniques for Acceleration on Unknown Trip Count and Early Exit Loops},
author = {Quoc Long Vinh Ta},
url = {https://mpslab-asu.github.io/publications/papers/Ta2022THESIS.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Ta2022THESIS.pptx, slides
},
year = {2022},
date = {2022-12-08},
urldate = {2022-12-08},
school = {Arizona State University},
keywords = {Coarse-Grained Reconfigurable Arrays},
pubstate = {published},
tppubtype = {mastersthesis}
}
40.
Edward Andert; Aviral Shrivastava
Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs Proceedings Article
In: Proceedings of the IEEE 25th International Conference on Intelligent Transportation Systems (ITSC), IEEE 2022.
BibTeX | Tags: Intelligent Transportation Systems | Links:
@inproceedings{Andert2022ITSC,
title = {Accurate Cooperative Sensor Fusion by Parameterized Covariance Generation for Sensing and Localization Pipelines in CAVs},
author = {Edward Andert and Aviral Shrivastava},
url = {https://mpslab-asu.github.io/publications/papers/Andert2022ITSC.pdf, pdf
https://mpslab-asu.github.io/publications/slides/Andert2022ITSC.pptx, slides
https://docs.google.com/presentation/d/1-i4m5GRfRn3lsFdo4RAhaY4qxdRgBfrX/edit?usp=sharing&ouid=101396061526471459814&rtpof=true&sd=true , slides},
year = {2022},
date = {2022-10-08},
urldate = {2022-10-08},
booktitle = {Proceedings of the IEEE 25th International Conference on Intelligent Transportation Systems (ITSC)},
organization = {IEEE},
keywords = {Intelligent Transportation Systems},
pubstate = {published},
tppubtype = {inproceedings}
}