Automatic Generation of Operation Tables for Fast Exploration of Bypasses in Embedded Processors Proceedings Article
In: DATE '06: Proceedings of the conference on Design, automation and test in Europe, pp. 1197-1202, 2006, (ISBN 3-9810801-0-6).
Architecture description language (ADL)-driven software toolkit generation for architectural exploration of programmable SOCs Journal Article
In: ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 3, pp. 626-658, 2006, (ISSN 1084-4309).
Retargetable pipeline hazard detection for partially bypassed processors Journal Article
In: vol. 14, pp. 791-801, 2006, (ISBN 1063-8210).
Compilation framework for code size reduction using reduced bit-width ISAs (rSAs) Journal Article
In: ACM Transactions on Design Automation of Electronic Systems, vol. 11, no. 1, pp. 123-146, 2006, (ISSN 1084-4309).
Compiler-in-Loop Exploration of Programmable Embedded Systems PhD Thesis
Donald Bren School of Information and Computer Sciences, 2006.
Compilation techniques for energy reduction in horizontally partitioned cache architectures Proceedings Article
In: CASES '05: Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems, pp. 90-96, 2005, (ISBN 1-59593-149-X).
Aggregating processor free time for energy reduction Proceedings Article
In: CODES+ISSS '05: Proceedings of the international conference on Hardware/software codesign and system synthesis, pp. 154-159, 2005, (ISBN 1-59593-161-9).
PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors Proceedings Article
In: DATE '05: Proceedings of the conference on Design, Automation and Test in Europe, 2005.
Compiler-in-the-Loop ADL-driven Early Architectural Exploration Proceedings Article
In: TECHCON 2005: Semiconductor Research Corporation, 2005.
Operation tables for scheduling in the presence of incomplete bypassing. Proceedings Article
In: CODES+ISSS, pp. 194-199, 2004.
Energy efficient code generation exploiting reduced bit-width instruction set architectures (rISA) Proceedings Article
In: ASP-DAC '04: Proceedings of the 2004 conference on Asia South Pacific design automation, pp. 475-477, 2004, (ISBN 0-7803-8175-0).
A Framework for GUI-driven Design Space Exploration of a MIPS4K-like processor Technical Report
University of California, Irvine 2003.
A design space exploration framework for reduced bit-width instruction set architecture (rISA) design Proceedings Article
In: ISSS '02: Proceedings of the 15th international symposium on System Synthesis, pp. 120-125, 2002, (ISBN 1-58113-576-9).
An Efficient Compiler Technique for Code Size Reduction Using Reduced Bit-Width ISAs Proceedings Article
In: DATE '02: Proceedings of the conference on Design, automation and test in Europe, pp. 402, 2002.
A customizable compiler framework for embedded systems Proceedings Article
In: In SCOPES, Springer, 2001.
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming Proceedings Article
In: VLSID '00: Proceedings of the 13th International Conference on VLSI Design, pp. 110, 2000, (ISBN 0-7695-0487-6).
Cyclebite: Extracting Task Graphs From Unstructured Compute-Programs Journal Article Forthcoming
In: IEEE Transactions on Computers, Forthcoming.
B-AWARE: Blockage Aware RSU Scheduling for 5G Enabled Autonomous Vehicles Journal Article
In: ACM Transactions on Embedded Computing Systems, vol. 22, iss. 5, no. 154, pp. 1-23, 0000.
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In: 0000.
DSP-MLIR: A Compiler for Digital Signal Processing in MLIR Masters Thesis
0000.