{"id":507,"date":"2021-07-21T13:13:42","date_gmt":"2021-07-21T20:13:42","guid":{"rendered":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/?page_id=507"},"modified":"2026-03-13T15:36:46","modified_gmt":"2026-03-13T22:36:46","slug":"507-2","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/","title":{"rendered":"Analog\/Mixed Signal VLSI Group"},"content":{"rendered":"\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<p class=\"wp-block-paragraph\">&nbsp;<\/p>\n\n\n\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1500\" height=\"872\" src=\"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2026\/03\/IMG_4615-1500x872.jpg\" alt=\"\" class=\"wp-image-992\" srcset=\"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2026\/03\/IMG_4615-1500x872.jpg 1500w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2026\/03\/IMG_4615-500x291.jpg 500w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2026\/03\/IMG_4615-1000x581.jpg 1000w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2026\/03\/IMG_4615-1536x893.jpg 1536w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2026\/03\/IMG_4615-2048x1191.jpg 2048w\" sizes=\"auto, (max-width: 1500px) 100vw, 1500px\" \/><\/figure>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image size-large\"><img loading=\"lazy\" decoding=\"async\" width=\"1500\" height=\"834\" src=\"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Picture5-1-1500x834.png\" alt=\"\" class=\"wp-image-522\" srcset=\"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Picture5-1-1500x834.png 1500w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Picture5-1-500x278.png 500w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Picture5-1-1000x556.png 1000w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Picture5-1-1536x854.png 1536w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Picture5-1.png 1962w\" sizes=\"auto, (max-width: 1500px) 100vw, 1500px\" \/><\/figure>\n<\/div>\n<\/div>\n\n\n\n<h4 class=\"wp-block-heading\">Welcome to the Analog\/Mixed Signal VLSI Research Group at Arizona State University. Our research interests are focused in the following broad areas:<\/h4>\n\n\n\n<div class=\"wp-block-image\">\r\n<figure class=\"alignleft\"><img loading=\"lazy\" decoding=\"async\" class=\"alignnone wp-image-435\" src=\"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Screen-Shot-2021-07-16-at-3.43.01-PM-500x449.png\" alt=\"\" width=\"400\" height=\"359\" srcset=\"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Screen-Shot-2021-07-16-at-3.43.01-PM-500x449.png 500w, https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-content\/uploads\/sites\/58\/2021\/07\/Screen-Shot-2021-07-16-at-3.43.01-PM.png 848w\" sizes=\"auto, (max-width: 400px) 100vw, 400px\" \/><\/figure>\r\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Analog and mixed signal integrated circuits&nbsp;<\/strong>with focus on high energy efficiency data converters and transceiver designs, and applications of machine learning for improving data converter performance&nbsp;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Intelligent sensors for personalized healthcare<\/strong> that involves design of in-memory computing analog neuromorphic circuits for wearable devices that monitor user health in real-time and provide actionable inference<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><strong>Hardware security&nbsp;<\/strong>with focus on primitives (true random number generators and physical unclonable functions), on-chip machine learning circuits for detecting security threats and techniques to address reliability of machine learning circuits<\/p>\n\n\n\n<p class=\"wp-block-paragraph\">&nbsp;<\/p>\n\n\n\n<p class=\"wp-block-paragraph\"><p>&nbsp;<\/p>\n<p>Motivated, prospective group members are encouraged email <strong>arindam.sanyal[at]asu.edu<\/strong> with resume and a brief description of research area(s) of interest.<\/p><\/p>\n","protected":false},"excerpt":{"rendered":"<p class=\"mb-2\">&nbsp; Welcome to the Analog\/Mixed Signal VLSI Research Group at Arizona State University. Our research interests are focused in the following broad areas: Analog and mixed signal integrated circuits&nbsp;with focus on high energy efficiency data converters and transceiver designs, and applications of machine learning for improving data converter performance&nbsp; Intelligent sensors for personalized healthcare that&#8230;<\/p>\n","protected":false},"author":135,"featured_media":0,"parent":0,"menu_order":7,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-507","page","type-page","status-publish","hentry"],"acf":[],"_links":{"self":[{"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/pages\/507","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/users\/135"}],"replies":[{"embeddable":true,"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/comments?post=507"}],"version-history":[{"count":0,"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/pages\/507\/revisions"}],"wp:attachment":[{"href":"https:\/\/labs.engineering.asu.edu\/mixedsignals\/wp-json\/wp\/v2\/media?parent=507"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}