2017 and earlier
[J1] B. Ghanavati, E. Abiri, M. R. Salehi, A. Keyhani and A. Sanyal, “LSB Split Capacitor SAR ADC with 99.2% Switching Energy Reduction”, Analog Integrated Circuits and Signal Processing, vol. 93, no. 2, pp. 375-382, 2017.
[J2] Imon Banerjee and Arindam Sanyal, “Statistical estimator for simultaneous noise and mismatch suppression in SAR ADC”, Electronics Letters, vol. 53, no. 12, pp. 6–8, 2017. [PDF]
[J3] Arindam Sanyal and Nan Sun, “An Energy-Efficient Hybrid SAR-VCO ∆Σ Capacitance-to-Digital Converter in 40nm CMOS”, IEEE Journal of Solid-State Circuits, vol. 52, no. 7, pp. 1966–1976, 2017. [PDF]
[J4] Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, and Nan Sun, “A 0.7-V 0.6-uW 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction”, IEEE Journal of Solid-State Circuits, vol. 52, no. 5, pp. 1388–1398, 2017. [PDF]
[J5] Arindam Sanyal and Nan Sun, “A second-order VCO-based delta sigma ADC using a modified DPLL”, Electronics Letters, vol. 52, no. 14, pp. 1204–1205, 2016.[PDF]
[J6] Long Chen, Kareem Ragab, Xiyuan Tang, Jeonggoo Song, Arindam Sanyal, and Nan Sun, “A 0.95-mW 6-b 700-Ms/s single-channel loop-unrolled SAR ADC in 40-nm CMOS”, IEEE TCAS-II, 2016.[PDF]
[J7] Arindam Sanyal, Xueyi Yu, Yanlong Zhang, and Nan Sun, “Fractional-N PLL with multi-element fractional divider for noise reduction”, Electronics Letters, vol. 52, no. 10, pp. 809–810, 2016.[PDF]
[J8] Arindam Sanyal and Nan Sun, “Dynamic element matching techniques for static and dynamic errors in continuous-time multi-bit ∆Σ modulators”, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), pp. 561–573, 2015.[PDF]
[J9] Arindam Sanyal, Long Chen, and Nan Sun, “Dynamic element matching with signal-independent element transition rates for multibit delta sigma modulators”, IEEE Transactions on Circuits and Systems–I, pp. 1325–1334, May, 2015.[PDF]
[J10] Manzur Rahman, Arindam Sanyal, and Nan Sun, “A novel hybrid radix-3/radix-2 SAR ADC with fast convergence and low hardware complexity”, IEEE Transactions on Circuits and Systems–II, pp. 426-430, May. 2015.[PDF]
[J11] Kareem Ragab, Long Chen, Arindam Sanyal, and Nan Sun, “Digital background calibration for pipelined ADCs based on comparator decision time quantization”, IEEE Transactions on Circuits and Systems–II, pp. 456-460, May. 2015.[PDF]
[J12] Arindam Sanyal, Peijun Wang and Nan Sun, “A thermometer-like mismatch shaping technique with minimum element transition activity for multi-bit delta-sigma DACs”, IEEE Transactions on Circuits and Systems–II, pp. 461–465, 2014.[PDF]
[J13] Arindam Sanyal and Nan Sun, “An energy-efficient, low frequency-dependence switching technique for SAR ADC”, IEEE Transactions on Circuits and Systems–II, pp. 294–298, 2014.[PDF]
[J14] Arindam Sanyal and Nan Sun, “A SAR ADC with 98% reduction in switching energy over conventional scheme”, Electronics Letters, pp. 248–250, Feb 2013.[PDF]
[C1] Vaishak Prathap, Sanjeev T. Chandrasekaran, and Arindam Sanyal, “2nd-Order VCO-Based CT ∆Σ ADC Architecture”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 687-690, 2017.[PDF]
[C2] Arindam Sanyal and Nan Sun, “A 18.5 fJ/step VCO-Based 0-1 MASH ∆Σ ADC with Digital Background Calibration”, IEEE Symposia on VLSI Technology and Circuits (VLSI-C), pp. 26–27, 2016.[PDF]
[C3] Long Chen, Arindam Sanyal, Ji Ma, and Nan Sun, “Comparator common-mode variation effects analysis and its application in SAR ADCs,”, IEEE International Symposium on Circuits and Systems (ISCAS), 2016.[PDF]
[C4] Arindam Sanyal and Nan Sun, “A 55fJ/conv-step VCO-Based ∆Σ Capacitance-to-Digital Converter in 40nm CMOS”, IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 385–388, 2016.[PDF]
[C5] Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, and Nan Sun, “A 10.5-b ENOB 645nW 100kS/s SAR ADC with Statistical Estimation Based Noise Reduction”, IEEE Custom Integrated Circuits Conference CICC, pp. 1–4, Sept. 2015.[PDF]
[C6] Arindam Sanyal, Kareem Ragab, Long Chen, T. R. Viswanathan, Shouli Yan and Nan Sun, “A hybrid SAR-VCO ∆Σ ADC with first-order noise shaping”, IEEE IEEE Custom Integrated Circuits Conference (CICC) , pp. 1–4, 2014.[PDF]
[C7] Long Chen, Arindam Sanyal, Ji Ma and Nan Sun, “A 24-uW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique”, IEEE European Solid-State Circuits Conference (ESSCIRC), pp. 219–222, 2014.[PDF]
[C8] Arindam Sanyal and Nan Sun, “An enhanced ISI shaping technique for multi-bit delta sigma DACs”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2341–2344, 2014.[PDF]
[C9] Arindam Sanyal and Nan Sun, “A low frequency-dependence, energy-efficient switching technique for bottom-plate sampled SAR ADC”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 297–300, 2014.[PDF]
[C10] Arindam Sanyal and Nan Sun, “A very high energy-efficiency switching technique for SAR ADCs”, IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 229–232, 2013.[PDF]
[C11] Wenjuan Guo, Youngchun Kim, Arindam Sanyal, Ahmed Tewfik and Nan Sun, “A single SAR ADC converting multi-channel sparse signals”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2235–2238, 2013.[PDF]
[C12] Arindam Sanyal and Nan Sun, “A Simple and Efficient Dithering Method for Vector Quantizer Based Mismatch-Shaped Delta Sigma DACs ”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 528–531, 2012.[PDF]
[C13] Arindam Sanyal and Tarun Kanti Bhattacharyya, “Maximizing the sequence length in a MASH Delta Sigma Modulator by dithering”, IEEE MTT-S International Microwave Symposium, pp. 1665–1668, June 2009.