{"id":132,"date":"2023-07-04T00:04:19","date_gmt":"2023-07-04T00:04:19","guid":{"rendered":"https:\/\/labs.engineering.asu.edu\/advent\/?page_id=132"},"modified":"2026-03-26T05:07:01","modified_gmt":"2026-03-26T05:07:01","slug":"projects","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/advent\/projects\/","title":{"rendered":"Projects"},"content":{"rendered":"\n<h2 class=\"wp-block-heading\">Current Projects<\/h2>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Novel architectures for PIM on FPGAs (Theme #1 and Theme #4)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with HPE<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Accelerating quantum control systems using FPGAs (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Abhi (University of Arkansas and LBL) and Dr. Nhan Tran (Fermilab)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Automatic DNN deployment on AMD Versal devices (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Using both AIE and AIE-ML engines<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">LLM acceleration on AMD Ryzen AI platform (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with AMD and Prof. Aviral Shrivastava (ASU)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Digital twin acceleration on AMD Versal devices (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Ashif Iqebal (ASU)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Accelerating medical applications on FPGAs (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Hassan Ghasemzadeh (ASU)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Enhancing programmability of domain-optimized FPGAs with custom hard blocks (Theme #1)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Agentic digital hardware verification (Theme #3)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Vidya Chhabria (ASU) <\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">DRAM PIM based acceleration for ML workloads (Theme #4)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Lizy John (UT Austin) and Prof. Jeeho Ryo (Fairleigh Dickinson University)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Path finding for novel chiplet-based disaggregated architectures (Theme #4)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Vidya Chhabria (ASU)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Sustainability and FPGAs (Theme #4)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Vidya Chhabria (ASU)<\/p>\n<\/div>\n<\/div>\n\n\n\n<h2 class=\"wp-block-heading\">Past Projects<\/h2>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Developing datasets and frameworks for ML for FPGA CAD (Theme #3)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Lizy John (UT Austin) and Prof. Callie Hao (Georgia Tech)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">SRAM PIM based accelerator and compiler for ML workloads (Theme #4)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Tony Nowatzki (UCLA) and Prof. Lizy John (UT Austin)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Cross-FPGA power prediction using ML (Theme #3)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Lizy John (UT Austin)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Architecture of next-gen reconfigurable devices (Theme #1)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Diana Marculescu (UT Austin)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Accelerating ML workloads using AMD Vitis AI Suite (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Comparing out-of-the-box performance of FPGAs using AMD Vitis AI Suite with TPUs<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Analyzing and comparing AI-optimized FPGAs (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">In collaboration with Prof. Andreas Gerstualer and Prof. Diana Maruclescu (UT Austin)<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Novel FPGA architectures for ML &#8211; Introducing Tensor Slices (Theme #1)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Work done while at University of Texas at Austin, in collaboration with University of Toronto<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Incorporating Processing-In-Memory on FPGAs &#8211; Introducing CoMeFa RAMs (Theme #1 and #4)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Work done while at University of Texas at Austin<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Benchmarks for FPGA architecture and CAD &#8211; Introducing Koios Benchmarks (Theme #1)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Work done while at University of Texas at Austin, in collaboration with University of Toronto and University of New Brunswick<\/p>\n<\/div>\n<\/div>\n\n\n\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-930feb06 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:66.66%\">\n<h4 class=\"wp-block-heading\">Accelerating Weightless Neural Networks on FPGAs (Theme #2)<\/h4>\n\n\n\n<p class=\"wp-block-paragraph\">Work done while at University of Texas at Austin, in collaboration with researchers from Brazil, Portugal and Texas<\/p>\n<\/div>\n<\/div>\n\n\n\n<p class=\"wp-block-paragraph\"><\/p>\n","protected":false},"excerpt":{"rendered":"<p class=\"mb-2\">Current Projects Novel architectures for PIM on FPGAs (Theme #1 and Theme #4) In collaboration with HPE Accelerating quantum control systems using FPGAs (Theme #2) In collaboration with Prof. Abhi (University of Arkansas and LBL) and Dr. Nhan Tran (Fermilab) Automatic DNN deployment on AMD Versal devices (Theme #2) Using both AIE and AIE-ML engines&#8230;<\/p>\n","protected":false},"author":228,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-132","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.8 - https:\/\/yoast.com\/product\/yoast-seo-wordpress\/ -->\n<title>Projects - Advent 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