{"id":130,"date":"2023-07-04T00:04:02","date_gmt":"2023-07-04T00:04:02","guid":{"rendered":"https:\/\/labs.engineering.asu.edu\/advent\/?page_id=130"},"modified":"2025-07-15T18:22:07","modified_gmt":"2025-07-15T18:22:07","slug":"themes","status":"publish","type":"page","link":"https:\/\/labs.engineering.asu.edu\/advent\/themes\/","title":{"rendered":"Themes"},"content":{"rendered":"\n<div class=\"wp-block-columns is-layout-flex wp-container-core-columns-is-layout-28f84493 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\">\n<figure class=\"wp-block-image aligncenter size-full\"><img loading=\"lazy\" decoding=\"async\" width=\"1120\" height=\"483\" src=\"https:\/\/labs.engineering.asu.edu\/advent\/wp-content\/uploads\/sites\/123\/2025\/01\/themes.png\" alt=\"\" class=\"wp-image-695\" srcset=\"https:\/\/labs.engineering.asu.edu\/advent\/wp-content\/uploads\/sites\/123\/2025\/01\/themes.png 1120w, https:\/\/labs.engineering.asu.edu\/advent\/wp-content\/uploads\/sites\/123\/2025\/01\/themes-300x129.png 300w, https:\/\/labs.engineering.asu.edu\/advent\/wp-content\/uploads\/sites\/123\/2025\/01\/themes-1024x442.png 1024w, https:\/\/labs.engineering.asu.edu\/advent\/wp-content\/uploads\/sites\/123\/2025\/01\/themes-768x331.png 768w\" sizes=\"auto, (max-width: 1120px) 100vw, 1120px\" \/><\/figure>\n<\/div>\n<\/div>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<div class=\"wp-block-columns alignfull is-layout-flex wp-container-core-columns-is-layout-28f84493 wp-block-columns-is-layout-flex\">\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.34%\"><\/div>\n\n\n\n<div class=\"wp-block-column is-vertically-aligned-center is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.34%\">\n<ul class=\"wp-block-list\">\n<li><strong>Theme #1:\u00a0<\/strong>Architecture and design of reconfigurable computing devices, Novel fabrics beyond traditional FPGAs, eFPGAs, Chiplet-based FPGAs, Improving the programmability of\u00a0reconfigurable computing devices<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Theme #2:\u00a0<\/strong>Hardware acceleration of machine learning (ML), Domain-specific acceleration of emerging workloads, New applications of reconfigurable computing such as digital twins and quantum control and simulation<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Theme #3:<\/strong>\u00a0Machine Learning (ML) for Hardware, Deploying ML and LLMs to improve architecture, design and verification of ASICs or FPGAs, developing datasets and frameworks for using ML easily in chip design<\/li>\n<\/ul>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong>Theme #4:&nbsp;<\/strong>Sustainable Computing, Energy efficient computing, Processing in\/near\/using memory, Combining non-Von Neumann computing with existing paradigms<\/li>\n<\/ul>\n<\/div>\n\n\n\n<div class=\"wp-block-column is-layout-flow wp-block-column-is-layout-flow\" style=\"flex-basis:33.33%\"><\/div>\n<\/div>\n","protected":false},"excerpt":{"rendered":"","protected":false},"author":228,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"_acf_changed":false,"footnotes":""},"class_list":["post-130","page","type-page","status-publish","hentry"],"acf":[],"yoast_head":"<!-- This site is optimized with the Yoast SEO plugin v27.5 - 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