Research – Old
Ph.D. Dissertation Research
Dissertation Title:
- Optimizing FPGA Architecture for Deep Learning Workloads
Highlights:
- Adding matrix multiplier blocks to FPGAs
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- Impact: The FPGA industry has developed similar blocks recently like Intel AI Tensor Block and Achronix Machine Learning Processor. Although these blocks do not support matrix multiplication natively, the fact that industry is finding similar solutions demonstrates that our research is on the right track.
- Incorporating compute-in-memory on FPGAs
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- Impact: Our paper proposing these memory blocks at FCCM’22 won the Best Paper Award, and companies like Rapid Silicon have expressed interest in this technology.
- Benchmarks for FPGA architecture research
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- Impact: Koios is being used by many researchers worldwide and also by companies like Efinix in their regression suite.
Poster:
- Click here for a poster that summarizes my PhD research
Other Current/Prior Research
- Developing a FPGA-like spatial accelerator for ML workloads using compute-enabled RAMs, with a focus on easy compilation
- Accelerating an entire different type of ML algorithm that does not use multiplication for computation: Weightless Neural Networks
- Predicting the power consumption of an application deployed on FPGA#1 using an ML model trained on a FPGA#2
Collaborations
- University of Toronto, Canada
- University of California Los Angeles
- University of New Brunswick, Canada
- International Institute of Technology, Bengaluru, India
- Federal University of Rio de Janeiro, Brazil
- Federal University of Reconcavo da Bahia, Brazil
Funding
My research at UT Austin has been funded by a NSF grant for 2020-2022. I was a Graduate Research Assistant at the University of Austin.
For 2022-2023, my research is funded by the UT Austin Graduate School Fellowship. I was awarded this fellowship because of an excellent publication record.
List of Publications
Peer Reviewed (first author)
CoMeFa: Deploying Compute-in-Memory on FPGAs for Deep Learning Acceleration [PDF]
Aman Arora, Atharva Bhamburkar, Aatman Borda, Tanmay Anand, Rishabh Sehgal, Bagus Hanindhito, Pierre-Emmanuel Gaillardon, Jaydeep Kulkarni, Lizy K. John
ACM Transactions on Reconfigurable Technology and Systems (TRETS), June 2023
Koios 2.0: Open-Source Deep Learning Benchmarks for FPGA Architecture and CAD Research [PDF]
Aman Arora, Andrew Boutros, Seyed Alireza Damghani, Karan Mathur, Vedant Mohanty, Tanmay Anand, Mohamed Elgammal, Kenneth B. Kent, Vaughn Betz, Lizy K. John
IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD), 2023
CoMeFa: Compute-in-Memory Blocks for FPGAs [PDF][Video]
Aman Arora, Tanmay Anand, Aatman Borda, Rishabh Sehgal, Bagus Hanindhito, Jaydeep Kulkarni and Lizy K. John
IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2022
(Acceptance Rate = 20.8%, Best Paper Award)
Tensor Slices: FPGA Building Blocks For The Deep Learning Era [PDF]
Aman Arora, Moinak Ghosh, Samidh Mehta, Vaughn Betz and Lizy K. John
ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2022
MathRAMs: Configurable Fused Compute-Memory Blocks for FPGAs (Poster) [PDF]
Aman Arora, Aatman Borda, Tanmay Anand, Bagus Hanindhito, Lizy K. John
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2022
Compute RAMs: Adaptable Compute and Storage Blocks for DL-Optimized FPGAs [PDF]
Aman Arora, Bagus Hanindhito, Lizy K. John
IEEE Asilomar Conference on Signals, Systems, and Computers (ASILOMAR), October 2021
(Acceptance Rate = 71.5%, Student Paper Contest Finalist, Top-8 out of 477)
Koios: A Deep Learning Benchmark Suite for FPGA Architecture and CAD Research [PDF][Video]
Aman Arora, Andrew Boutros, Daniel Rauch, Aishwarya Rajen, Aatman Borda, Seyed Alireza Damghani, Samidh Mehta, Sangram Kate, Pragnesh Patel, Kenneth B. Kent, Vaughn Betz, Lizy K. John
IEEE International Conference on Field-Programmable Logic and Applications (FPL), August 2021
(Acceptance Rate = 22%)
Tensor Slices to the Rescue: Supercharging ML Acceleration on FPGAs [PDF][Video]
Aman Arora, Samidh Mehta, Vaughn Betz, Lizy K. John
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2021
(Acceptance Rate = 23%)
Hamamu: Specializing FPGAs for ML Applications by Adding Hard Matrix Multiplier Blocks [PDF][Video]
Aman Arora, Zhigang Wei, Lizy K. John
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2020
(Acceptance Rate = 24%)
The Case for Hard Matrix Multiplier Blocks in an FPGA (Poster) [PDF]
Aman Arora, Zhigang Wei, Lizy K. John
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2020
(Acceptance Rate = 25% for papers, 30% for posters)
Peer Reviewed (co-authored)
HLSDataset: Open-Source Dataset for ML-Assisted FPGA Design using High Level Synthesis []
Zhigang Wei, Aman Arora, Ruihao Li, Lizy K. John
IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), July 2023
COIN: Combinational Intelligent Networks (Poster) []
Igor D. S. Miranda, Aman Arora, Zachary Susskind, Josias S. A. Souza, Mugdha P. Jadhao, Luis A. Q. Villon, Diego L. C. Dutra, Priscila M. V. Lima, Felipe M. G. França, Mauricio Breternitz and Lizy K. John
IEEE International Conference on Application-specific Systems, Architectures, and Processors (ASAP), July 2023
An FPGA-Based Weightless Neural Network for Edge Network Intrusion Detection (Poster) [PDF]
Zachary Susskind, Aman Arora, Alan Bacellar, Diego L. C. Dutra, Igor D. S. Miranda, Mauricio Breternitz Jr., Priscila M. V. Lima, Felipe M. G. Franca, Lizy K. John
ACM International Symposium on Field-Programmable Gate Arrays (FPGA), February 2023
Weightless Neural Networks for Efficient Edge Inference [PDF]
Zachary Susskind, Aman Arora, Igor D. S. Miranda, Luis A. Q. Villon, Rafael F. Katopodis, Leandro S. de Araujo, Diego L. C. Dutra, Priscila M. V. Lima, Felipe M. G. Franca, Mauricio Breternitz Jr., Lizy K. John
Parallel Architectures and Compilation Techniques (PACT), October 2022
Pruning Weightless Neural Networks [PDF]
Zachary Susskind, Alan T. L. Bacellar, Aman Arora, Luis A. Q. Villon, Renan Mendanha, Leandro S. de Araujo, Diego L. C. Dutra, Priscila M. V. Lima, Felipe M. G. Franca, Igor D. S. Miranda, Mauricio Breternitz Jr., Lizy K. John
European Symposium on Artificial Neural Networks, Computational Intelligence and Machine Learning (ESANN), October 2022
LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks [PDF]
Igor Dantas Dos Santos Miranda, Aman Arora, Zachary Susskind, Lizy K. John, Luis Armando Quintanilla Villon, Rafael Fontella Katopodis, Diego Leonel Cadette Dutra, Priscila Machado Vieira Lima, Felipe Maia Galvao Franca, Leandro Santiago de Araujo, Mauricio Breternitz Jr.
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2022
(Acceptance Rate = TBD, Best Paper Candidate)
Hardware-aware 3D Model Workload Selection and Characterization for Graphics and ML Applications (Poster) [PDF]
Ruihao Li, Aman Arora, Sikan Li, Qinzhe Wu and Lizy K. John
IEEE International Symposium on Quality Electronic Design (ISQED), April 2022
LogGen: A Parameterized Generator for Designing Floating-Point Logarithm Units for Deep Learning [PDF]
Pragnesh Patel, Aman Arora, Earl Swartzlander and Lizy K. John
IEEE International Symposium on Quality Electronic Design (ISQED), April 2022
Design Space Exploration of Softmax Implementations [PDF]
Zhigang Wei, Aman Arora, Lizy K. John
IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2020
(Acceptance Rate = 24%)
Other Publications
A TPU-like Design for FPGA Benchmarking [PDF]
Aman Arora, Bagus Hanindhito, Harsh Gugale, Lizy K. John
Technical Report, Class Project
A novel approach to sideband signal verification with a reusable and configurable UVM agent
Aman Arora and Jeetendra Gupta
NTECH 2016 (NVIDIA’s internal tech conference)
Compile time parameter distribution for highly reusable testbenches
Aman Arora and Mark Glasser
Synopsys Users Group (SNUG) Silicon Valley 2015
RTL-Agent Switch: Implementation and Applications
Aman Arora, Nathan Wooster, Pavan Mula, Rob Porter
Synopsys Users Group (SNUG) Austin 2015
Method and apparatus to debug simulation failures for [on-chip] scan compression patterns
Anurag Jindal and Aman Arora
Defensive Publication (IPCOM #000185968D)
Testing memories through functional interface using BIST, with 100% test quality and 0% timing impact
Anurag Jindal and Aman Arora
Defensive Publication (IPCOM #000185974D)
Method and apparatus for robust verification of test views of library cells
Nikila K and Aman Arora
Defensive Publication (IPCOM #000191493D)
Testing flash memories
Aman Arora, Akshat Gupta & Mayuri Agarwal
White Paper on EETimes/Techonline
Automated approach for efficient DFT pattern generation and simulation debug
Anurag Jindal, Aman Arora
Freescale Design Competitiveness Conference 2008
