I’ve worked in the industry for several years and have done lot of exciting work with so many wonderful people. I’ve worked in the areas of Design-For-Test, Design Verification, SoC Security, SoC Boot, Verification Methodology and Infrastructure, High-Speed IOs, GPU Deep Learning Architecture.

Rapid Silicon

JUN 2022 – Aug 2022

Intern – AI Hardware, CTO Group

  • Implementing in-memory compute on FPGAs. Integrating an in-memory compute based accelerator with a soft RISC processor on an FPGA.
  • Exploring changes to BRAM and DSP architectures for future Rapid Silicon products and updating architecture specification files


JUN 2012 – DEC 2020

Deep Learning GPU Performance Architect

  • Modelling next-gen features in an analytical GPU simulator and studying the end-to-end impact using state-of-the-art workloads/DNNs.
  • Silicon bringup of DL training related features on Ampere architecture. Looking at performance of memory-limited workloads, with emphasis on L2 cache strategies.
  • Performance analysis of state-of-the-art DNNs, comparing Silicon performance with theoretical expectations and identifying/suggesting improvements. Developing a tool to automate this process

High Speed I/O Verification Lead

  • Worked unit-level verification of NVLINK high speed IO controller. Also responsible for communication and coordination with external IP customers.
  • Led a team of about 20 people, spread across California, Texas and India, for the verification of PCIe Gen4 controllers. Involved in all aspects – verification planning, schedule management, resource allocation, tracking deliverables, reporting metrics, task prioritization. Also handled external communication with EDA VIP vendors.
  • Drove the methodology and architecture of the testbench architect verification of PCIe Gen4 controllers; the testbench was UVM based and used by multiple DUTs.

SoC Verification, Methodology and Infrastructure Engineer

  • Worked on System Security verification and Boot ROM verification of a Tegra SoC. Interacted with multiple teams to track security verification across various blocks. Also led the silicon bringup activities for system security features on this chip.
  • Worked on development and betterment of verification infrastructure, reuse strategy and flows.
  • Actively worked on several components (including VIP) of a new verification architecture based on UVM and C++, which is now used across the Tegra organization at NVIDIA.


JUN 2011 – AUG 2011

Atom Validation and Emulation Intern

  • Development, simulation and synthesis of designs used on the FPGA-based validation boards
  • Modelling of several hardware interfaces in C and using the SV-DPI to simulate them with RTL

Freescale (now, NXP)

JAN 2008 – JUL 2010

SoC Design-For-Test (DFT) Engineer

  • Memory BIST generation and verification, and Logic BIST verification
  • Incorporation and verification of memory repair and flash memory testing infrastructure
  • Scan Stuck-at automatic test pattern generation (ATPG) and simulation on gate-level netlist
  • Test mode entry & test clocking verification on RTL, and DFT design rule checks
  • Conversion of VCD into tester format patterns (WGL) and resimulation of WGL
  • Generation of BSDL and JTAG test patterns, and verification on RTL and gate-level netlists
  • Mentoring recruits and facilitating training process by conducting knowledge transfer sessions

Atrenta (now, Synopsys)

JUL 2007 – DEC 2007

Software Engineer, Design-For-Test, Spyglass

  • Incident fixes and enhancements in SpyGlass DFT policy
  • Development and verification of the SER (Soft Error Rate) custom policy

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